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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
| 30 | #include <arch/mm/asid.h> |
30 | #include <mm/asid.h> |
| 31 | #include <mm/tlb.h> |
31 | #include <mm/tlb.h> |
| 32 | #include <mm/page.h> |
32 | #include <mm/page.h> |
| 33 | #include <mm/as.h> |
33 | #include <mm/as.h> |
| 34 | #include <arch/cp0.h> |
34 | #include <arch/cp0.h> |
| 35 | #include <panic.h> |
35 | #include <panic.h> |
| Line 492... | Line 492... | ||
| 492 | 492 | ||
| 493 | interrupts_restore(ipl); |
493 | interrupts_restore(ipl); |
| 494 | cp0_entry_hi_write(hi_save.value); |
494 | cp0_entry_hi_write(hi_save.value); |
| 495 | } |
495 | } |
| 496 | 496 | ||
| 497 | /** Invalidate TLB entry for specified page belonging to specified address space. |
497 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
| 498 | * |
498 | * |
| 499 | * @param asid Address space identifier. |
499 | * @param asid Address space identifier. |
| 500 | * @param page Page whose TLB entry is to be invalidated. |
500 | * @param page First page whose TLB entry is to be invalidated. |
| - | 501 | * @param cnt Number of entries to invalidate. |
|
| 501 | */ |
502 | */ |
| 502 | void tlb_invalidate_page(asid_t asid, __address page) |
503 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
| 503 | { |
504 | { |
| - | 505 | int i; |
|
| 504 | ipl_t ipl; |
506 | ipl_t ipl; |
| 505 | entry_lo_t lo0, lo1; |
507 | entry_lo_t lo0, lo1; |
| 506 | entry_hi_t hi, hi_save; |
508 | entry_hi_t hi, hi_save; |
| 507 | tlb_index_t index; |
509 | tlb_index_t index; |
| 508 | 510 | ||
| 509 | ASSERT(asid != ASID_INVALID); |
511 | ASSERT(asid != ASID_INVALID); |
| 510 | 512 | ||
| 511 | hi_save.value = cp0_entry_hi_read(); |
513 | hi_save.value = cp0_entry_hi_read(); |
| 512 | ipl = interrupts_disable(); |
514 | ipl = interrupts_disable(); |
| 513 | 515 | ||
| - | 516 | for (i = 0; i < cnt; i++) { |
|
| 514 | hi.value = 0; |
517 | hi.value = 0; |
| 515 | prepare_entry_hi(&hi, asid, page); |
518 | prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
| 516 | cp0_entry_hi_write(hi.value); |
519 | cp0_entry_hi_write(hi.value); |
| 517 | 520 | ||
| 518 | tlbp(); |
521 | tlbp(); |
| 519 | index.value = cp0_index_read(); |
522 | index.value = cp0_index_read(); |
| - | 523 | ||
| - | 524 | if (!index.p) { |
|
| - | 525 | /* Entry was found, index register contains valid index. */ |
|
| - | 526 | tlbr(); |
|
| 520 | 527 | ||
| 521 | if (!index.p) { |
- | |
| 522 | /* Entry was found, index register contains valid index. */ |
- | |
| 523 | tlbr(); |
- | |
| 524 | - | ||
| 525 | lo0.value = cp0_entry_lo0_read(); |
528 | lo0.value = cp0_entry_lo0_read(); |
| 526 | lo1.value = cp0_entry_lo1_read(); |
529 | lo1.value = cp0_entry_lo1_read(); |
| 527 | 530 | ||
| 528 | lo0.v = 0; |
531 | lo0.v = 0; |
| 529 | lo1.v = 0; |
532 | lo1.v = 0; |
| 530 | 533 | ||
| 531 | cp0_entry_lo0_write(lo0.value); |
534 | cp0_entry_lo0_write(lo0.value); |
| 532 | cp0_entry_lo1_write(lo1.value); |
535 | cp0_entry_lo1_write(lo1.value); |
| 533 | 536 | ||
| 534 | tlbwi(); |
537 | tlbwi(); |
| - | 538 | } |
|
| 535 | } |
539 | } |
| 536 | 540 | ||
| 537 | interrupts_restore(ipl); |
541 | interrupts_restore(ipl); |
| 538 | cp0_entry_hi_write(hi_save.value); |
542 | cp0_entry_hi_write(hi_save.value); |
| 539 | } |
543 | } |