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    /* It is not assumed by default */
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    /* It is not assumed by default */
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    interrupts_disable();
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    interrupts_disable();
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    /* Initialize dispatch table */
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    /* Initialize dispatch table */
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    exception_init();
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    exception_init();
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    interrupt_init();
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    arc_init();
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    arc_init();
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    /* Copy the exception vectors to the right places */
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    /* Copy the exception vectors to the right places */
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    memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
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    memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
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    memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
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    memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
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    memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
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    memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
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- 
 
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    interrupt_init();
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    /*
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    /*
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     * Switch to BEV normal level so that exception vectors point to the kernel.
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     * Switch to BEV normal level so that exception vectors point to the kernel.
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     * Clear the error level.
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     * Clear the error level.
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     */
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     */
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    cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
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    cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
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    /*
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    /*
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     * Mask all interrupts
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     * Mask all interrupts
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     */
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     */
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    cp0_mask_all_int();
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    cp0_mask_all_int();
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    /*
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    /*
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     * Unmask hardware clock interrupt.
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     * Unmask hardware clock interrupt.
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     */
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     */
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    cp0_unmask_int(TIMER_IRQ);
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    cp0_unmask_int(TIMER_IRQ);
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    /*
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     * Start hardware clock.
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     */
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    cp0_compare_write(cp0_compare_value + cp0_count_read());
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    console_init();
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    console_init();
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    debugger_init();
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    debugger_init();
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}
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}
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void arch_post_mm_init(void)
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void arch_post_mm_init(void)