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Line 40... Line 40...
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#include <panic.h>
40
#include <panic.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
42
#include <arch/barrier.h>
43
#include <memstr.h>
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#include <memstr.h>
44
 
44
 
45
static void set_vhpt_environment(void);
45
static void set_environment(void);
46
 
46
 
47
/** Initialize ia64 virtual address translation subsystem. */
47
/** Initialize ia64 virtual address translation subsystem. */
48
void page_arch_init(void)
48
void page_arch_init(void)
49
{
49
{
50
    page_operations = &page_ht_operations;
50
    page_operations = &page_ht_operations;
51
    pk_disable();
51
    pk_disable();
52
    set_vhpt_environment();
52
    set_environment();
53
}
53
}
54
 
54
 
55
/** Initialize VHPT and region registers. */
55
/** Initialize VHPT and region registers. */
56
void set_vhpt_environment(void)
56
void set_environment(void)
57
{
57
{
58
    region_register rr;
58
    region_register rr;
59
    pta_register pta;  
59
    pta_register pta;  
60
    int i;
60
    int i;
61
   
61
   
Line 85... Line 85...
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        srlz_i();
85
        srlz_i();
86
        srlz_d();
86
        srlz_d();
87
    }
87
    }
88
 
88
 
89
    /*
89
    /*
90
     * Allocate VHPT and invalidate all its entries.
-
 
91
     */
-
 
92
    page_ht = (pte_t *) frame_alloc(VHPT_WIDTH - FRAME_WIDTH, FRAME_KA);
-
 
93
    memsetb((__address) page_ht, VHPT_SIZE, 0);
-
 
94
    ht_invalidate_all();   
-
 
95
   
-
 
96
    /*
-
 
97
     * Set up PTA register.
90
     * Set up PTA register.
98
     */
91
     */
99
    pta.word = pta_read();
92
    pta.word = pta_read();
100
    pta.map.ve = 0;                   /* disable VHPT walker */
93
    pta.map.ve = 0;                   /* disable VHPT walker */
101
    pta.map.vf = 1;                   /* large entry format */
94
    pta.map.vf = 1;                   /* large entry format */
102
    pta.map.size = VHPT_WIDTH;
95
    pta.map.size = VHPT_WIDTH;
103
    pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT;
96
    pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
104
    pta_write(pta.word);
97
    pta_write(pta.word);
105
    srlz_i();
98
    srlz_i();
106
    srlz_d();
99
    srlz_d();
107
}
100
}
108
 
101
 
Line 111... Line 104...
111
 * Interrupts must be disabled.
104
 * Interrupts must be disabled.
112
 *
105
 *
113
 * @param page Address of virtual page including VRN bits.
106
 * @param page Address of virtual page including VRN bits.
114
 * @param asid Address space identifier.
107
 * @param asid Address space identifier.
115
 *
108
 *
116
 * @return Head of VHPT collision chain for page and asid.
109
 * @return VHPT entry address.
117
 */
110
 */
118
pte_t *vhpt_hash(__address page, asid_t asid)
111
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
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{
112
{
120
    region_register rr_save, rr;
113
    region_register rr_save, rr;
121
    index_t vrn;
114
    index_t vrn;
122
    rid_t rid;
115
    rid_t rid;
123
    pte_t *t;
116
    vhpt_entry_t *v;
124
 
117
 
125
    vrn = page >> VRN_SHIFT;
118
    vrn = page >> VRN_SHIFT;
126
    rid = ASID2RID(asid, vrn);
119
    rid = ASID2RID(asid, vrn);
127
   
120
   
128
    rr_save.word = rr_read(vrn);
121
    rr_save.word = rr_read(vrn);
129
    if (rr_save.map.rid == rid) {
122
    if (rr_save.map.rid == rid) {
130
        /*
123
        /*
131
         * The RID is already in place, compute thash and return.
124
         * The RID is already in place, compute thash and return.
132
         */
125
         */
133
        t = (pte_t *) thash(page);
126
        v = (vhpt_entry_t *) thash(page);
134
        return t;
127
        return v;
135
    }
128
    }
136
   
129
   
137
    /*
130
    /*
138
     * The RID must be written to some region register.
131
     * The RID must be written to some region register.
139
     * To speed things up, register indexed by vrn is used.
132
     * To speed things up, register indexed by vrn is used.
140
     */
133
     */
141
    rr.word = rr_save.word;
134
    rr.word = rr_save.word;
142
    rr.map.rid = rid;
135
    rr.map.rid = rid;
143
    rr_write(vrn, rr.word);
136
    rr_write(vrn, rr.word);
144
    srlz_i();
137
    srlz_i();
145
    t = (pte_t *) thash(page);
138
    v = (vhpt_entry_t *) thash(page);
146
    rr_write(vrn, rr_save.word);
139
    rr_write(vrn, rr_save.word);
147
    srlz_i();
140
    srlz_i();
148
    srlz_d();
141
    srlz_d();
149
 
142
 
150
    return t;
143
    return v;
151
}
144
}
152
 
145
 
153
/** Compare ASID and VPN against PTE.
146
/** Compare ASID and VPN against PTE.
154
 *
147
 *
155
 * Interrupts must be disabled.
148
 * Interrupts must be disabled.
Line 157... Line 150...
157
 * @param page Address of virtual page including VRN bits.
150
 * @param page Address of virtual page including VRN bits.
158
 * @param asid Address space identifier.
151
 * @param asid Address space identifier.
159
 *
152
 *
160
 * @return True if page and asid match the page and asid of t, false otherwise.
153
 * @return True if page and asid match the page and asid of t, false otherwise.
161
 */
154
 */
162
bool vhpt_compare(__address page, asid_t asid, pte_t *t)
155
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
163
{
156
{
164
    region_register rr_save, rr;   
157
    region_register rr_save, rr;   
165
    index_t vrn;
158
    index_t vrn;
166
    rid_t rid;
159
    rid_t rid;
167
    bool match;
160
    bool match;
168
 
161
 
169
    ASSERT(t);
162
    ASSERT(v);
170
 
163
 
171
    vrn = page >> VRN_SHIFT;
164
    vrn = page >> VRN_SHIFT;
172
    rid = ASID2RID(asid, vrn);
165
    rid = ASID2RID(asid, vrn);
173
   
166
   
174
    rr_save.word = rr_read(vrn);
167
    rr_save.word = rr_read(vrn);
175
    if (rr_save.map.rid == rid) {
168
    if (rr_save.map.rid == rid) {
176
        /*
169
        /*
177
         * The RID is already in place, compare ttag with t and return.
170
         * The RID is already in place, compare ttag with t and return.
178
         */
171
         */
179
        return ttag(page) == t->present.tag.tag_word;
172
        return ttag(page) == v->present.tag.tag_word;
180
    }
173
    }
181
   
174
   
182
    /*
175
    /*
183
     * The RID must be written to some region register.
176
     * The RID must be written to some region register.
184
     * To speed things up, register indexed by vrn is used.
177
     * To speed things up, register indexed by vrn is used.
185
     */
178
     */
186
    rr.word = rr_save.word;
179
    rr.word = rr_save.word;
187
    rr.map.rid = rid;
180
    rr.map.rid = rid;
188
    rr_write(vrn, rr.word);
181
    rr_write(vrn, rr.word);
189
    srlz_i();
182
    srlz_i();
190
    match = (ttag(page) == t->present.tag.tag_word);
183
    match = (ttag(page) == v->present.tag.tag_word);
191
    rr_write(vrn, rr_save.word);
184
    rr_write(vrn, rr_save.word);
192
    srlz_i();
185
    srlz_i();
193
    srlz_d();
186
    srlz_d();
194
 
187
 
195
    return match;      
188
    return match;      
Line 201... Line 194...
201
 * @param page Virtual address of the page mapped by the entry.
194
 * @param page Virtual address of the page mapped by the entry.
202
 * @param asid Address space identifier of the address space to which page belongs.
195
 * @param asid Address space identifier of the address space to which page belongs.
203
 * @param frame Physical address of the frame to wich page is mapped.
196
 * @param frame Physical address of the frame to wich page is mapped.
204
 * @param flags Different flags for the mapping.
197
 * @param flags Different flags for the mapping.
205
 */
198
 */
206
void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags)
199
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
207
{
200
{
208
    region_register rr_save, rr;   
201
    region_register rr_save, rr;   
209
    index_t vrn;
202
    index_t vrn;
210
    rid_t rid;
203
    rid_t rid;
211
    __u64 tag;
204
    __u64 tag;
212
 
205
 
213
    ASSERT(t);
206
    ASSERT(v);
214
 
207
 
215
    vrn = page >> VRN_SHIFT;
208
    vrn = page >> VRN_SHIFT;
216
    rid = ASID2RID(asid, vrn);
209
    rid = ASID2RID(asid, vrn);
217
   
210
   
218
    /*
211
    /*
Line 229... Line 222...
229
    srlz_d();
222
    srlz_d();
230
   
223
   
231
    /*
224
    /*
232
     * Clear the entry.
225
     * Clear the entry.
233
     */
226
     */
234
    t->word[0] = 0;
227
    v->word[0] = 0;
235
    t->word[1] = 0;
228
    v->word[1] = 0;
236
    t->word[2] = 0;
229
    v->word[2] = 0;
237
    t->word[3] = 0;
230
    v->word[3] = 0;
238
   
231
   
239
    t->present.p = true;
232
    v->present.p = true;
240
    t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
233
    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
241
    t->present.a = false;   /* not accessed */
234
    v->present.a = false;   /* not accessed */
242
    t->present.d = false;   /* not dirty */
235
    v->present.d = false;   /* not dirty */
243
    t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
236
    v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
244
    t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
237
    v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
245
    t->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
238
    v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
246
    t->present.ppn = frame >> PPN_SHIFT;
239
    v->present.ppn = frame >> PPN_SHIFT;
247
    t->present.ed = false;  /* exception not deffered */
240
    v->present.ed = false;  /* exception not deffered */
248
    t->present.ps = PAGE_WIDTH;
241
    v->present.ps = PAGE_WIDTH;
249
    t->present.key = 0;
242
    v->present.key = 0;
250
    t->present.tag.tag_word = tag;
243
    v->present.tag.tag_word = tag;
251
    t->present.next = NULL;
-
 
252
}
244
}