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| Line 27... | Line 27... | ||
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #ifndef __ia64_REGISTER_H__ |
29 | #ifndef __ia64_REGISTER_H__ |
| 30 | #define __ia64_REGISTER_H__ |
30 | #define __ia64_REGISTER_H__ |
| 31 | 31 | ||
| 32 | #ifndef __ASM__ |
- | |
| 33 | #include <arch/types.h> |
- | |
| 34 | #endif |
- | |
| 35 | - | ||
| 36 | #define CR_IVR_MASK 0xf |
32 | #define CR_IVR_MASK 0xf |
| 37 | #define PSR_IC_MASK 0x2000 |
33 | #define PSR_IC_MASK 0x2000 |
| 38 | #define PSR_I_MASK 0x4000 |
34 | #define PSR_I_MASK 0x4000 |
| 39 | #define PSR_PK_MASK 0x8000 |
35 | #define PSR_PK_MASK 0x8000 |
| 40 | 36 | ||
| Line 43... | Line 39... | ||
| 43 | #define PSR_IT_MASK 0x0000001000000000 |
39 | #define PSR_IT_MASK 0x0000001000000000 |
| 44 | 40 | ||
| 45 | #define PSR_CPL_SHIFT 32 |
41 | #define PSR_CPL_SHIFT 32 |
| 46 | #define PSR_CPL_MASK_SHIFTED 3 |
42 | #define PSR_CPL_MASK_SHIFTED 3 |
| 47 | 43 | ||
| - | 44 | #define PFM_MASK (~0x3fffffffff) |
|
| - | 45 | ||
| - | 46 | #define RSC_MODE_MASK 3 |
|
| - | 47 | #define RSC_PL_MASK 12 |
|
| - | 48 | ||
| 48 | /** Application registers. */ |
49 | /** Application registers. */ |
| 49 | #define AR_KR0 0 |
50 | #define AR_KR0 0 |
| 50 | #define AR_KR1 1 |
51 | #define AR_KR1 1 |
| 51 | #define AR_KR2 2 |
52 | #define AR_KR2 2 |
| 52 | #define AR_KR3 3 |
53 | #define AR_KR3 3 |
| Line 118... | Line 119... | ||
| 118 | #define CR_LRR0 80 |
119 | #define CR_LRR0 80 |
| 119 | #define CR_LRR1 81 |
120 | #define CR_LRR1 81 |
| 120 | /* CR82-CR127 reserved */ |
121 | /* CR82-CR127 reserved */ |
| 121 | 122 | ||
| 122 | #ifndef __ASM__ |
123 | #ifndef __ASM__ |
| - | 124 | ||
| - | 125 | #include <arch/types.h> |
|
| - | 126 | ||
| - | 127 | /** Processor Status Register. */ |
|
| - | 128 | union psr { |
|
| - | 129 | __u64 value; |
|
| - | 130 | struct { |
|
| - | 131 | unsigned : 1; |
|
| - | 132 | unsigned be : 1; /**< Big-Endian data accesses. */ |
|
| - | 133 | unsigned up : 1; /**< User Performance monitor enable. */ |
|
| - | 134 | unsigned ac : 1; /**< Alignment Check. */ |
|
| - | 135 | unsigned mfl : 1; /**< Lower floating-point register written. */ |
|
| - | 136 | unsigned mfh : 1; /**< Upper floating-point register written. */ |
|
| - | 137 | unsigned : 7; |
|
| - | 138 | unsigned ic : 1; /**< Interruption Collection. */ |
|
| - | 139 | unsigned i : 1; /**< Interrupt Bit. */ |
|
| - | 140 | unsigned pk : 1; /**< Protection Key enable. */ |
|
| - | 141 | unsigned : 1; |
|
| - | 142 | unsigned dt : 1; /**< Data address Translation. */ |
|
| - | 143 | unsigned dfl : 1; /**< Disabled Floating-point Low register set. */ |
|
| - | 144 | unsigned dfh : 1; /**< Disabled Floating-point High register set. */ |
|
| - | 145 | unsigned sp : 1; /**< Secure Performance monitors. */ |
|
| - | 146 | unsigned pp : 1; /**< Privileged Performance monitor enable. */ |
|
| - | 147 | unsigned di : 1; /**< Disable Instruction set transition. */ |
|
| - | 148 | unsigned si : 1; /**< Secure Interval timer. */ |
|
| - | 149 | unsigned db : 1; /**< Debug Breakpoint fault. */ |
|
| - | 150 | unsigned lp : 1; /**< Lower Privilege transfer trap. */ |
|
| - | 151 | unsigned tb : 1; /**< Taken Branch trap. */ |
|
| - | 152 | unsigned rt : 1; /**< Register Stack Translation. */ |
|
| - | 153 | unsigned : 4; |
|
| - | 154 | unsigned cpl : 2; /**< Current Privilege Level. */ |
|
| - | 155 | unsigned is : 1; /**< Instruction Set. */ |
|
| - | 156 | unsigned mc : 1; /**< Machine Check abort mask. */ |
|
| - | 157 | unsigned it : 1; /**< Instruction address Translation. */ |
|
| - | 158 | unsigned id : 1; /**< Instruction Debug fault disable. */ |
|
| - | 159 | unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */ |
|
| - | 160 | unsigned dd : 1; /**< Data Debug fault disable. */ |
|
| - | 161 | unsigned ss : 1; /**< Single Step enable. */ |
|
| - | 162 | unsigned ri : 2; /**< Restart Instruction. */ |
|
| - | 163 | unsigned ed : 1; /**< Exception Deferral. */ |
|
| - | 164 | unsigned bn : 1; /**< Register Bank. */ |
|
| - | 165 | unsigned ia : 1; /**< Disable Instruction Access-bit faults. */ |
|
| - | 166 | } __attribute__ ((packed)); |
|
| - | 167 | }; |
|
| - | 168 | typedef union psr psr_t; |
|
| - | 169 | ||
| - | 170 | /** Register Stack Configuration Register */ |
|
| - | 171 | union rsc { |
|
| - | 172 | __u64 value; |
|
| - | 173 | struct { |
|
| - | 174 | unsigned mode : 2; |
|
| - | 175 | unsigned pl : 2; /**< Privilege Level. */ |
|
| - | 176 | unsigned be : 1; /**< Big-endian. */ |
|
| - | 177 | unsigned : 11; |
|
| - | 178 | unsigned loadrs : 14; |
|
| - | 179 | } __attribute__ ((packed)); |
|
| - | 180 | }; |
|
| - | 181 | typedef union rsc rsc_t; |
|
| - | 182 | ||
| 123 | /** External Interrupt Vector Register */ |
183 | /** External Interrupt Vector Register */ |
| 124 | union cr_ivr { |
184 | union cr_ivr { |
| 125 | __u8 vector; |
185 | __u8 vector; |
| 126 | __u64 value; |
186 | __u64 value; |
| 127 | }; |
187 | }; |