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40 | 40 | ||
41 | #define PSR_DT_MASK (1<<17) |
41 | #define PSR_DT_MASK (1<<17) |
42 | #define PSR_RT_MASK (1<<27) |
42 | #define PSR_RT_MASK (1<<27) |
43 | #define PSR_IT_MASK 0x0000001000000000 |
43 | #define PSR_IT_MASK 0x0000001000000000 |
44 | 44 | ||
- | 45 | #define PSR_CPL_SHIFT 32 |
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- | 46 | #define PSR_CPL_MASK_SHIFTED 3 |
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- | 47 | ||
45 | /** Application registers. */ |
48 | /** Application registers. */ |
46 | #define AR_KR0 0 |
49 | #define AR_KR0 0 |
47 | #define AR_KR1 1 |
50 | #define AR_KR1 1 |
48 | #define AR_KR2 2 |
51 | #define AR_KR2 2 |
49 | #define AR_KR3 3 |
52 | #define AR_KR3 3 |