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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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/*
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/*
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 * Advanced Programmable Interrupt Controller for SMP systems.
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 * Advanced Programmable Interrupt Controller for SMP systems.
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 * Tested on:
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 * Tested on:
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 *  Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs
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 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
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 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
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 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
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 *  VMware Workstation 5.5 with 2 CPUs
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 *  VMware Workstation 5.5 with 2 CPUs
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 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
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 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
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 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
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 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
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 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
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 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
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/** Initialize Local APIC. */
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/** Initialize Local APIC. */
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void l_apic_init(void)
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void l_apic_init(void)
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{
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{
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    lvt_error_t error;
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    lvt_error_t error;
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    lvt_lint_t lint;
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    lvt_lint_t lint;
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    tpr_t tpr;
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    svr_t svr;
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    svr_t svr;
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    icr_t icr;
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    icr_t icr;
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    tdcr_t tdcr;
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    tdcr_t tdcr;
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    lvt_tm_t tm;
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    lvt_tm_t tm;
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    ldr_t ldr;
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    ldr_t ldr;
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    /* Initialize LVT LINT1 register. */
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    /* Initialize LVT LINT1 register. */
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    lint.value = l_apic[LVT_LINT1];
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    lint.value = l_apic[LVT_LINT1];
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    lint.masked = true;
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    lint.masked = true;
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    l_apic[LVT_LINT1] = lint.value;
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    l_apic[LVT_LINT1] = lint.value;
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- 
 
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    /* Task Priority Register initialization. */
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    tpr.value = l_apic[TPR];
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    tpr.pri_sc = 0;
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    tpr.pri = 0;
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    l_apic[TPR] = tpr.value;
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    /* Spurious-Interrupt Vector Register initialization. */
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    /* Spurious-Interrupt Vector Register initialization. */
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    svr.value = l_apic[SVR];
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    svr.value = l_apic[SVR];
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    svr.vector = VECTOR_APIC_SPUR;
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    svr.vector = VECTOR_APIC_SPUR;
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    svr.lapic_enabled = true;
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    svr.lapic_enabled = true;
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    svr.focus_checking = true;
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    l_apic[SVR] = svr.value;
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    l_apic[SVR] = svr.value;
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    l_apic[TPR] &= TPRClear;
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 - 
 
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    if (CPU->arch.family >= 6)
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    if (CPU->arch.family >= 6)
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        enable_l_apic_in_msr();
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        enable_l_apic_in_msr();
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    /* Interrupt Command Register initialization. */
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    /* Interrupt Command Register initialization. */
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    icr.lo = l_apic[ICRlo];
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    icr.lo = l_apic[ICRlo];