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| Rev 633 | Rev 1024 | ||
|---|---|---|---|
| Line 57... | Line 57... | ||
| 57 | #else |
57 | #else |
| 58 | __asm__ volatile ("decl %0\n" : "=m" (val->count)); |
58 | __asm__ volatile ("decl %0\n" : "=m" (val->count)); |
| 59 | #endif /* CONFIG_SMP */ |
59 | #endif /* CONFIG_SMP */ |
| 60 | } |
60 | } |
| 61 | 61 | ||
| 62 | static inline count_t atomic_inc_pre(atomic_t *val) |
62 | static inline count_t atomic_postinc(atomic_t *val) |
| 63 | { |
63 | { |
| 64 | count_t r; |
64 | count_t r; |
| 65 | 65 | ||
| 66 | __asm__ volatile ( |
66 | __asm__ volatile ( |
| 67 | "movl $1, %0\n" |
67 | "movl $1, %0\n" |
| Line 70... | Line 70... | ||
| 70 | ); |
70 | ); |
| 71 | 71 | ||
| 72 | return r; |
72 | return r; |
| 73 | } |
73 | } |
| 74 | 74 | ||
| 75 | static inline count_t atomic_dec_pre(atomic_t *val) |
75 | static inline count_t atomic_postdec(atomic_t *val) |
| 76 | { |
76 | { |
| 77 | count_t r; |
77 | count_t r; |
| 78 | 78 | ||
| 79 | __asm__ volatile ( |
79 | __asm__ volatile ( |
| 80 | "movl $-1, %0\n" |
80 | "movl $-1, %0\n" |
| Line 83... | Line 83... | ||
| 83 | ); |
83 | ); |
| 84 | 84 | ||
| 85 | return r; |
85 | return r; |
| 86 | } |
86 | } |
| 87 | 87 | ||
| 88 | #define atomic_inc_post(val) (atomic_inc_pre(val)+1) |
88 | #define atomic_preinc(val) (atomic_postinc(val)+1) |
| 89 | #define atomic_dec_post(val) (atomic_dec_pre(val)-1) |
89 | #define atomic_predec(val) (atomic_postdec(val)-1) |
| 90 | 90 | ||
| 91 | static inline __u32 test_and_set(atomic_t *val) { |
91 | static inline __u32 test_and_set(atomic_t *val) { |
| 92 | __u32 v; |
92 | __u32 v; |
| 93 | 93 | ||
| 94 | __asm__ volatile ( |
94 | __asm__ volatile ( |