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#include <arch/types.h>
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#include <arch/types.h>
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#include <config.h>
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#include <config.h>
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#include <proc/thread.h>
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#include <arch/ega.h>
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#include <arch/ega.h>
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#include <genarch/i8042/i8042.h>
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#include <genarch/i8042/i8042.h>
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#include <arch/i8254.h>
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#include <arch/i8254.h>
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#include <arch/i8259.h>
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#include <arch/i8259.h>
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#include <genarch/acpi/acpi.h>
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#include <genarch/acpi/acpi.h>
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#include <panic.h>
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#include <panic.h>
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#include <interrupt.h>
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#include <interrupt.h>
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#include <arch/syscall.h>
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#include <arch/syscall.h>
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#include <arch/debugger.h>
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#include <arch/debugger.h>
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#include <syscall/syscall.h>
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/** Disable I/O on non-privileged levels
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/** Disable I/O on non-privileged levels
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 *
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 *
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 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
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 * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
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 */
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 */
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void calibrate_delay_loop(void)
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void calibrate_delay_loop(void)
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{
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{
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    i8254_calibrate_delay_loop();
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    i8254_calibrate_delay_loop();
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    i8254_normal_operation();
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    i8254_normal_operation();
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}
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}
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/** Set Thread-local-storeage pointer
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 *
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 * TLS pointer is set in FS register. Unfortunately the 64-bit
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 * part can be set only in CPL0 mode.
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 *
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 * The specs says, that on %fs:0 there is stored contents of %fs register,
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 * we need not to go to CPL0 to read it.
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 */
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__native sys_tls_set(__native addr)
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{
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    THREAD->tls = addr;
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    write_msr(AMD_MSR_FS, addr);
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    return 0;
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}