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#ifndef __amd64_ATOMIC_H__
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#ifndef __amd64_ATOMIC_H__
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#define __amd64_ATOMIC_H__
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#define __amd64_ATOMIC_H__
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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/barrier.h>
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#include <preemption.h>
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typedef struct { volatile __u64 count; } atomic_t;
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typedef struct { volatile __u64 count; } atomic_t;
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static inline void atomic_set(atomic_t *val, __u64 i)
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static inline void atomic_set(atomic_t *val, __u64 i)
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{
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{
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    return v;
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    return v;
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}
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}
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/** AMD64 specific fast spinlock */
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extern void spinlock_arch(volatile int *val);
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static inline void atomic_lock_arch(atomic_t *val)
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{
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    __u64 tmp;
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    preemption_disable();
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    __asm__ volatile (
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        "0:;"
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#ifdef CONFIG_HT
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        "pause;" /* Pentium 4's HT love this instruction */
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#endif
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        "mov %0, %1;"
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        "testq %1, %1;"
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        "jnz 0b;"       /* Leightweight looping on locked spinlock */
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        "incq %1;"      /* now use the atomic operation */
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        "xchgq %0, %1;"
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        "testq %1, %1;"
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        "jnz 0b;"
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                : "=m"(val->count),"=r"(tmp)
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        );
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    /*
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     * Prevent critical section code from bleeding out this way up.
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     */
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    CS_ENTER_BARRIER();
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}
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#endif
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#endif