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Rev 3675 | Rev 4377 | ||
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Line 40... | Line 40... | ||
40 | #include <mm/page.h> |
40 | #include <mm/page.h> |
41 | #include <mm/slab.h> |
41 | #include <mm/slab.h> |
42 | #include <arch/types.h> |
42 | #include <arch/types.h> |
43 | #include <debug.h> |
43 | #include <debug.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | #include <func.h> |
45 | #include <string.h> |
46 | #include <arch/asm.h> |
46 | #include <arch/asm.h> |
- | 47 | #include <sysinfo/sysinfo.h> |
|
47 | 48 | ||
48 | #define SABRE_INTERNAL_REG 0 |
49 | #define SABRE_INTERNAL_REG 0 |
49 | #define PSYCHO_INTERNAL_REG 2 |
50 | #define PSYCHO_INTERNAL_REG 2 |
50 | 51 | ||
51 | #define OBIO_IMR_BASE 0x200 |
52 | #define OBIO_IMR_BASE 0x200 |
Line 106... | Line 107... | ||
106 | 107 | ||
107 | pci->model = PCI_SABRE; |
108 | pci->model = PCI_SABRE; |
108 | pci->op = &pci_sabre_ops; |
109 | pci->op = &pci_sabre_ops; |
109 | pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size); |
110 | pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size); |
110 | 111 | ||
- | 112 | /* |
|
- | 113 | * Set sysinfo data needed by the uspace OBIO driver. |
|
- | 114 | */ |
|
- | 115 | sysinfo_set_item_val("obio.base.physical", NULL, paddr); |
|
- | 116 | sysinfo_set_item_val("kbd.cir.obio", NULL, 1); |
|
- | 117 | ||
111 | return pci; |
118 | return pci; |
112 | } |
119 | } |
113 | 120 | ||
114 | 121 | ||
115 | /** Initialize the Psycho PCI controller. |
122 | /** Initialize the Psycho PCI controller. |
Line 147... | Line 154... | ||
147 | 154 | ||
148 | pci->model = PCI_PSYCHO; |
155 | pci->model = PCI_PSYCHO; |
149 | pci->op = &pci_psycho_ops; |
156 | pci->op = &pci_psycho_ops; |
150 | pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size); |
157 | pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size); |
151 | 158 | ||
- | 159 | /* |
|
- | 160 | * Set sysinfo data needed by the uspace OBIO driver. |
|
- | 161 | */ |
|
- | 162 | sysinfo_set_item_val("obio.base.physical", NULL, paddr); |
|
- | 163 | sysinfo_set_item_val("kbd.cir.obio", NULL, 1); |
|
- | 164 | ||
152 | return pci; |
165 | return pci; |
153 | } |
166 | } |
154 | 167 | ||
155 | void obio_enable_interrupt(pci_t *pci, int inr) |
168 | void obio_enable_interrupt(pci_t *pci, int inr) |
156 | { |
169 | { |
Line 168... | Line 181... | ||
168 | ofw_tree_property_t *prop; |
181 | ofw_tree_property_t *prop; |
169 | 182 | ||
170 | /* |
183 | /* |
171 | * First, verify this is a PCI node. |
184 | * First, verify this is a PCI node. |
172 | */ |
185 | */ |
173 | ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0); |
186 | ASSERT(str_cmp(ofw_tree_node_name(node), "pci") == 0); |
174 | 187 | ||
175 | /* |
188 | /* |
176 | * Determine PCI controller model. |
189 | * Determine PCI controller model. |
177 | */ |
190 | */ |
178 | prop = ofw_tree_getprop(node, "model"); |
191 | prop = ofw_tree_getprop(node, "model"); |
179 | if (!prop || !prop->value) |
192 | if (!prop || !prop->value) |
180 | return NULL; |
193 | return NULL; |
181 | 194 | ||
182 | if (strcmp(prop->value, "SUNW,sabre") == 0) { |
195 | if (str_cmp(prop->value, "SUNW,sabre") == 0) { |
183 | /* |
196 | /* |
184 | * PCI controller Sabre. |
197 | * PCI controller Sabre. |
185 | * This model is found on UltraSPARC IIi based machines. |
198 | * This model is found on UltraSPARC IIi based machines. |
186 | */ |
199 | */ |
187 | return pci_sabre_init(node); |
200 | return pci_sabre_init(node); |
188 | } else if (strcmp(prop->value, "SUNW,psycho") == 0) { |
201 | } else if (str_cmp(prop->value, "SUNW,psycho") == 0) { |
189 | /* |
202 | /* |
190 | * PCI controller Psycho. |
203 | * PCI controller Psycho. |
191 | * Used on UltraSPARC II based processors, for instance, |
204 | * Used on UltraSPARC II based processors, for instance, |
192 | * on Ultra 60. |
205 | * on Ultra 60. |
193 | */ |
206 | */ |