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Rev 4383 Rev 4433
Line 65... Line 65...
65
.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
65
.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
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.global instruction_access_exception_tl0
66
.global instruction_access_exception_tl0
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instruction_access_exception_tl0:
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instruction_access_exception_tl0:
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	PREEMPTIBLE_HANDLER instruction_access_exception
68
	PREEMPTIBLE_HANDLER instruction_access_exception
69
 
69
 
-
 
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/* TT = 0x09, TL = 0, instruction_access_mmu_miss */
-
 
71
.org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
-
 
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.global instruction_access_mmu_miss_handler_tl0
-
 
73
	ba fast_instruction_access_mmu_miss_handler_tl0
-
 
74
	nop
-
 
75
 
70
/* TT = 0x0a, TL = 0, instruction_access_error */
76
/* TT = 0x0a, TL = 0, instruction_access_error */
71
.org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE
77
.org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE
72
.global instruction_access_error_tl0
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.global instruction_access_error_tl0
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instruction_access_error_tl0:
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instruction_access_error_tl0:
74
	PREEMPTIBLE_HANDLER instruction_access_error
80
	PREEMPTIBLE_HANDLER instruction_access_error
Line 174... Line 180...
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.org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE
180
.org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE
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.global data_access_exception_tl0
181
.global data_access_exception_tl0
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data_access_exception_tl0:
182
data_access_exception_tl0:
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	PREEMPTIBLE_HANDLER data_access_exception
183
	PREEMPTIBLE_HANDLER data_access_exception
178
 
184
 
-
 
185
/* TT = 0x31, TL = 0, data_access_mmu_miss */
-
 
186
.org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
-
 
187
.global data_access_mmu_miss_tl0
-
 
188
data_access_mmu_miss_tl0:
-
 
189
	ba fast_data_access_mmu_miss_handler_tl0
-
 
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	nop
-
 
191
 
179
/* TT = 0x32, TL = 0, data_access_error */
192
/* TT = 0x32, TL = 0, data_access_error */
180
.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
193
.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
181
.global data_access_error_tl0
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.global data_access_error_tl0
182
data_access_error_tl0:
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data_access_error_tl0:
183
	PREEMPTIBLE_HANDLER data_access_error
196
	PREEMPTIBLE_HANDLER data_access_error
Line 394... Line 407...
394
.global instruction_access_exception_tl1
407
.global instruction_access_exception_tl1
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instruction_access_exception_tl1:
408
instruction_access_exception_tl1:
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	wrpr %g0, 1, %tl
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	wrpr %g0, 1, %tl
397
	PREEMPTIBLE_HANDLER instruction_access_exception
410
	PREEMPTIBLE_HANDLER instruction_access_exception
398
 
411
 
-
 
412
/* TT = 0x09, TL > 0, instruction_access_mmu_miss */
-
 
413
.org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
-
 
414
.global instruction_access_mmu_miss_handler_tl1
-
 
415
	wrpr %g0, 1, %tl
-
 
416
	ba fast_instruction_access_mmu_miss_handler_tl0
-
 
417
	nop
-
 
418
 
399
/* TT = 0x0a, TL > 0, instruction_access_error */
419
/* TT = 0x0a, TL > 0, instruction_access_error */
400
.org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE
420
.org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE
401
.global instruction_access_error_tl1
421
.global instruction_access_error_tl1
402
instruction_access_error_tl1:
422
instruction_access_error_tl1:
403
	wrpr %g0, 1, %tl
423
	wrpr %g0, 1, %tl
Line 471... Line 491...
471
data_access_exception_tl1:
491
data_access_exception_tl1:
472
	/*wrpr %g0, 1, %tl
492
	/*wrpr %g0, 1, %tl
473
	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
493
	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
474
	PREEMPTIBLE_HANDLER data_access_exception*/
494
	PREEMPTIBLE_HANDLER data_access_exception*/
475
 
495
 
-
 
496
/* TT = 0x31, TL > 0, data_access_mmu_miss */
-
 
497
.org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
-
 
498
.global data_access_mmu_miss_tl1
-
 
499
data_access_mmu_miss_tl1:
-
 
500
	ba fast_data_access_mmu_miss_handler_tl1
-
 
501
	nop
-
 
502
 
-
 
503
 
476
/* TT = 0x32, TL > 0, data_access_error */
504
/* TT = 0x32, TL > 0, data_access_error */
477
.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
505
.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
478
.global data_access_error_tl1
506
.global data_access_error_tl1
479
data_access_error_tl1:
507
data_access_error_tl1:
480
	wrpr %g0, 1, %tl
508
	wrpr %g0, 1, %tl