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| Rev 4129 | Rev 4130 | ||
|---|---|---|---|
| Line 40... | Line 40... | ||
| 40 | #define MMU_FSA_SIZE 128 |
40 | #define MMU_FSA_SIZE 128 |
| 41 | 41 | ||
| 42 | #ifndef __ASM__ |
42 | #ifndef __ASM__ |
| 43 | 43 | ||
| 44 | #include <arch/mm/tte.h> |
44 | #include <arch/mm/tte.h> |
| - | 45 | #include <print.h> |
|
| 45 | #include <arch/mm/mmu.h> |
46 | #include <arch/mm/mmu.h> |
| 46 | #include <arch/mm/page.h> |
47 | #include <arch/mm/page.h> |
| 47 | #include <arch/asm.h> |
48 | #include <arch/asm.h> |
| 48 | #include <arch/barrier.h> |
49 | #include <arch/barrier.h> |
| 49 | #include <arch/types.h> |
50 | #include <arch/types.h> |
| Line 137... | Line 138... | ||
| 137 | */ |
138 | */ |
| 138 | static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { |
139 | static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { |
| 139 | __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); |
140 | __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); |
| 140 | } |
141 | } |
| 141 | 142 | ||
| 142 | /** |
- | |
| 143 | * Installs a locked TLB entry in kernel address space. |
- | |
| 144 | * |
- | |
| 145 | * @param vaddr VA of the page to be demapped |
- | |
| 146 | * @param ra real address the page is mapped to |
- | |
| 147 | * @param cacheable should the page be cacheble? |
- | |
| 148 | * @param privileged should the mapping be privileged? |
- | |
| 149 | * @param executable should the memory mapped be executable? |
- | |
| 150 | * @param writable should the memory mapped be writable? |
- | |
| 151 | * @param size code of the page size |
- | |
| 152 | * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
- | |
| 153 | */ |
- | |
| 154 | static inline void mmu_map_perm_addr(uintptr_t vaddr, uintptr_t ra, |
- | |
| 155 | bool cacheable, bool privileged, bool executable, |
- | |
| 156 | bool writable, unsigned size, unsigned mmu_flags) { |
- | |
| 157 | - | ||
| 158 | tte_data_t data; |
- | |
| 159 | data.value = 0; |
- | |
| 160 | - | ||
| 161 | data.v = true; |
- | |
| 162 | data.ra = ra; |
- | |
| 163 | data.cp = data.cv = cacheable; |
- | |
| 164 | data.p = privileged; |
- | |
| 165 | data.x = executable; |
- | |
| 166 | data.w = writable; |
- | |
| 167 | data.size = size; |
- | |
| 168 | - | ||
| 169 | __hypercall_fast4(MMU_MAP_PERM_ADDR, vaddr, 0, data.value, mmu_flags); |
- | |
| 170 | } |
- | |
| 171 | - | ||
| 172 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
143 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
| 173 | extern void fast_data_access_mmu_miss(unative_t, istate_t *); |
144 | extern void fast_data_access_mmu_miss(unative_t, istate_t *); |
| 174 | extern void fast_data_access_protection(unative_t, istate_t *); |
145 | extern void fast_data_access_protection(unative_t, istate_t *); |
| 175 | 146 | ||
| 176 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
147 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |