WebSVN – HelenOS – Diff – //branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tlb.h

 #define MMU_FSA_ALIGNMENT   64
 #define MMU_FSA_SIZE        128
 #ifndef __ASM__
-#include <arch/mm/sun4v/tte.h>
+#include <arch/mm/tte.h>
-#include <arch/mm/sun4v/mmu.h>
+#include <arch/mm/mmu.h>
 #include <arch/mm/page.h>
 #include <arch/asm.h>
 #include <arch/barrier.h>
 #include <arch/types.h>
 #include <arch/register.h>
 #include <arch/cpu.h>
+#include <arch/sun4v/hypercall.h>
 /**
  * Structure filled by hypervisor (or directly CPU, if implemented so) when
  * a MMU fault occurs. The structure describes the exact condition which
- * has caused the fault;
+ * has caused the fault.
  */
 typedef struct mmu_fault_status_area {
     uint64_t ift;       /**< Instruction fault type (IFT) */
     uint64_t ifa;       /**< Instruction fault address (IFA) */
     uint64_t ifc;       /**< Instruction fault context (IFC) */
     uint64_t dfa;       /**< Data fault address (DFA) */
     uint64_t dfc;       /**< Data fault context (DFC) */
     uint8_t reserved2[0x28];
 } __attribute__ ((packed)) mmu_fault_status_area_t;
-#if 0
-union tlb_context_reg {
-    uint64_t v;
-    struct {
-        unsigned long : 51;
-        unsigned context : 13;      /**< Context/ASID. */
-    } __attribute__ ((packed));
-};
-typedef union tlb_context_reg tlb_context_reg_t;
-/** I-/D-TLB Data In/Access Register type. */
-typedef tte_data_t tlb_data_t;
-/** I-/D-TLB Data Access Address in Alternate Space. */
-#if defined (US)
-union tlb_data_access_addr {
+#define DTLB_MAX_LOCKED_ENTRIES     8
-    uint64_t value;
-    struct {
-        uint64_t : 55;
-        unsigned tlb_entry : 6;
-        unsigned : 3;
-    } __attribute__ ((packed));
-};
-typedef union tlb_data_access_addr dtlb_data_access_addr_t;
-typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
-typedef union tlb_data_access_addr itlb_data_access_addr_t;
-typedef union tlb_data_access_addr itlb_tag_read_addr_t;
+/** Bit width of the TLB-locked portion of kernel address space. */
-#elif defined (US3)
+#define KERNEL_PAGE_WIDTH       22  /* 4M */
 /*
- * In US3, I-MMU and D-MMU have different formats of the data
- * access register virtual address. In the corresponding
- * structures the member variable for the entry number is
- * called "local_tlb_entry" - it contrasts with the "tlb_entry"
- * for the US data access register VA structure. The rationale
- * behind this is to prevent careless mistakes in the code
- * caused by setting only the entry number and not the TLB
- * number in the US3 code (when taking the code from US).
- */
-union dtlb_data_access_addr {
-    uint64_t value;
-    struct {
-        uint64_t : 45;
-        unsigned : 1;
-        unsigned tlb_number : 2;
-        unsigned : 4;
-        unsigned local_tlb_entry : 9;
-        unsigned : 3;
-    } __attribute__ ((packed));
-};
-typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
-typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
-union itlb_data_access_addr {
-    uint64_t value;
-    struct {
-        uint64_t : 45;
-        unsigned : 1;
-        unsigned tlb_number : 2;
-        unsigned : 6;
-        unsigned local_tlb_entry : 7;
-        unsigned : 3;
-    } __attribute__ ((packed));
-};
-typedef union itlb_data_access_addr itlb_data_access_addr_t;
-typedef union itlb_data_access_addr itlb_tag_read_addr_t;
-#endif
-/** I-/D-TLB Tag Read Register. */
-union tlb_tag_read_reg {
-    uint64_t value;
-    struct {
-        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
-        unsigned context : 13;  /**< Context identifier. */
-    } __attribute__ ((packed));
-};
-typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
-typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
-/** TLB Demap Operation Address. */
-union tlb_demap_addr {
-    uint64_t value;
-    struct {
-        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
-#if defined (US)
-        unsigned : 6;       /**< Ignored. */
-        unsigned type : 1;  /**< The type of demap operation. */
-#elif defined (US3)
-        unsigned : 5;       /**< Ignored. */
-        unsigned type: 2;   /**< The type of demap operation. */
-#endif
-        unsigned context : 2;   /**< Context register selection. */
-        unsigned : 4;       /**< Zero. */
-    } __attribute__ ((packed));
-};
-typedef union tlb_demap_addr tlb_demap_addr_t;
-/** TLB Synchronous Fault Status Register. */
-union tlb_sfsr_reg {
-    uint64_t value;
-    struct {
-#if defined (US)
-        unsigned long : 40; /**< Implementation dependent. */
-        unsigned asi : 8;   /**< ASI. */
-        unsigned : 2;
-        unsigned ft : 7;    /**< Fault type. */
-#elif defined (US3)
-        unsigned long : 39; /**< Implementation dependent. */
-        unsigned nf : 1;    /**< Non-faulting load. */
-        unsigned asi : 8;   /**< ASI. */
-        unsigned tm : 1;    /**< I-TLB miss. */
-        unsigned : 3;       /**< Reserved. */
-        unsigned ft : 5;    /**< Fault type. */
-#endif
-        unsigned e : 1;     /**< Side-effect bit. */
-        unsigned ct : 2;    /**< Context Register selection. */
+ * Reading and writing context registers.
-        unsigned pr : 1;    /**< Privilege bit. */
-        unsigned w : 1;     /**< Write bit. */
-        unsigned ow : 1;    /**< Overwrite bit. */
-        unsigned fv : 1;    /**< Fault Valid bit. */
-    } __attribute__ ((packed));
-};
-typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
-#if defined (US3)
-/*
+ *
- * Functions for determining the number of entries in TLBs. They either return
+ * Note that UltraSPARC Architecture-compatible processors do not require
- * a constant value or a value based on the CPU autodetection.
+ * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an
- */
-/**
- * Determine the number of entries in the DMMU's small TLB.
- */
-static inline uint16_t tlb_dsmall_size(void)
-{
-    return 16;
-}
-/**
- * Determine the number of entries in each DMMU's big TLB.
- */
-static inline uint16_t tlb_dbig_size(void)
+ * MMU register for proper operation.
-{
-    return 512;
-}
-/**
- * Determine the number of entries in the IMMU's small TLB.
- */
+ *
-static inline uint16_t tlb_ismall_size(void)
-{
-    return 16;
-}
-/**
- * Determine the number of entries in the IMMU's big TLB.
  */
-static inline uint16_t tlb_ibig_size(void)
-{
-    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
-        return 512;
-    else
-        return 128;
-}
-#endif
 /** Read MMU Primary Context Register.
+ *
- * @return      Current value of Primary Context Register.
+ * @return  Current value of Primary Context Register.
  */
 static inline uint64_t mmu_primary_context_read(void)
+{
-    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
+    return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
+}
 /** Write MMU Primary Context Register.
+ *
- * @param v     New value of Primary Context Register.
+ * @param v New value of Primary Context Register.
  */
 static inline void mmu_primary_context_write(uint64_t v)
+{
-    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
+    asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
-    flush_pipeline();
+}
 /** Read MMU Secondary Context Register.
+ *
- * @return      Current value of Secondary Context Register.
+ * @return  Current value of Secondary Context Register.
  */
 static inline uint64_t mmu_secondary_context_read(void)
+{
-    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
+    return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
+}
-/** Write MMU Primary Context Register.
+/** Write MMU Secondary Context Register.
+ *
- * @param v     New value of Primary Context Register.
+ * @param v New value of Secondary Context Register.
  */
 static inline void mmu_secondary_context_write(uint64_t v)
+{
-    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
+    asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
-    flush_pipeline();
-}
-#if defined (US)
-/** Read IMMU TLB Data Access Register.
- *
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified IMMU TLB Data Access
- *          Register.
- */
-static inline uint64_t itlb_data_access_read(index_t entry)
-{
-    itlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_entry = entry;
-    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
-}
-/** Write IMMU TLB Data Access Register.
- *
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
- */
-static inline void itlb_data_access_write(index_t entry, uint64_t value)
-{
-    itlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_entry = entry;
-    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-    flush_pipeline();
-}
-/** Read DMMU TLB Data Access Register.
- *
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified DMMU TLB Data Access
- *          Register.
- */
-static inline uint64_t dtlb_data_access_read(index_t entry)
-{
-    dtlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_entry = entry;
-    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
-}
-/** Write DMMU TLB Data Access Register.
- *
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
- */
-static inline void dtlb_data_access_write(index_t entry, uint64_t value)
-{
-    dtlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_entry = entry;
-    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
-    membar();
-}
-/** Read IMMU TLB Tag Read Register.
- *
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified IMMU TLB Tag Read Register.
- */
-static inline uint64_t itlb_tag_read_read(index_t entry)
-{
-    itlb_tag_read_addr_t tag;
-    tag.value = 0;
-    tag.tlb_entry = entry;
-    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
-}
-/** Read DMMU TLB Tag Read Register.
- *
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified DMMU TLB Tag Read Register.
- */
-static inline uint64_t dtlb_tag_read_read(index_t entry)
-{
-    dtlb_tag_read_addr_t tag;
-    tag.value = 0;
-    tag.tlb_entry = entry;
-    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
-}
-#elif defined (US3)
-/** Read IMMU TLB Data Access Register.
- *
- * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified IMMU TLB Data Access
- *          Register.
- */
-static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
-{
-    itlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
-}
-/** Write IMMU TLB Data Access Register.
- * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
- */
-static inline void itlb_data_access_write(int tlb, index_t entry,
-    uint64_t value)
-{
-    itlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-    flush_pipeline();
-}
-/** Read DMMU TLB Data Access Register.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified DMMU TLB Data Access
- *          Register.
- */
-static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
-{
-    dtlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
-}
-/** Write DMMU TLB Data Access Register.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
- */
-static inline void dtlb_data_access_write(int tlb, index_t entry,
-    uint64_t value)
-{
-    dtlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
-    membar();
-}
-/** Read IMMU TLB Tag Read Register.
- *
- * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified IMMU TLB Tag Read Register.
- */
-static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
-{
-    itlb_tag_read_addr_t tag;
-    tag.value = 0;
-    tag.tlb_number = tlb;
-    tag.local_tlb_entry = entry;
-    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
-}
-/** Read DMMU TLB Tag Read Register.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified DMMU TLB Tag Read Register.
- */
-static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
-{
-    dtlb_tag_read_addr_t tag;
-    tag.value = 0;
-    tag.tlb_number = tlb;
-    tag.local_tlb_entry = entry;
-    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
-}
-#endif
-/** Write IMMU TLB Tag Access Register.
- *
- * @param v     Value to be written.
- */
-static inline void itlb_tag_access_write(uint64_t v)
-{
-    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
-    flush_pipeline();
-}
-/** Read IMMU TLB Tag Access Register.
- *
- * @return      Current value of IMMU TLB Tag Access Register.
- */
-static inline uint64_t itlb_tag_access_read(void)
-{
-    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
-}
-/** Write DMMU TLB Tag Access Register.
- *
- * @param v     Value to be written.
- */
-static inline void dtlb_tag_access_write(uint64_t v)
-{
-    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
-    membar();
-}
-/** Read DMMU TLB Tag Access Register.
- *
- * @return      Current value of DMMU TLB Tag Access Register.
- */
-static inline uint64_t dtlb_tag_access_read(void)
-{
-    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
-}
-/** Write IMMU TLB Data in Register.
- *
- * @param v     Value to be written.
- */
-static inline void itlb_data_in_write(uint64_t v)
-{
-    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
-    flush_pipeline();
-}
-/** Write DMMU TLB Data in Register.
- *
- * @param v     Value to be written.
- */
-static inline void dtlb_data_in_write(uint64_t v)
-{
-    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
-    membar();
-}
-/** Read ITLB Synchronous Fault Status Register.
- *
- * @return      Current content of I-SFSR register.
- */
-static inline uint64_t itlb_sfsr_read(void)
-{
-    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
-}
-/** Write ITLB Synchronous Fault Status Register.
- *
- * @param v     New value of I-SFSR register.
- */
-static inline void itlb_sfsr_write(uint64_t v)
-{
-    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
-    flush_pipeline();
-}
-/** Read DTLB Synchronous Fault Status Register.
- *
- * @return      Current content of D-SFSR register.
- */
-static inline uint64_t dtlb_sfsr_read(void)
-{
-    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
-}
-/** Write DTLB Synchronous Fault Status Register.
- *
- * @param v     New value of D-SFSR register.
- */
-static inline void dtlb_sfsr_write(uint64_t v)
-{
-    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
-    membar();
-}
-/** Read DTLB Synchronous Fault Address Register.
- *
- * @return      Current content of D-SFAR register.
- */
-static inline uint64_t dtlb_sfar_read(void)
-{
-    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
+}
 /** Perform IMMU TLB Demap Operation.
+ *
  * @param type      Selects between context and page demap (and entire MMU
  *          demap.
  * @param page      Address which is on the page to be demapped.
  */
 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
+{
-    tlb_demap_addr_t da;
-    page_address_t pg;
-    da.value = 0;
-    pg.address = page;
-    da.type = type;
-    da.context = context_encoding;
-    da.vpn = pg.vpn;
-    /* da.value is the address within the ASI */
-    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
-    flush_pipeline();
+}
 /** Perform DMMU TLB Demap Operation.
+ *
- * @param type      Selects between context and page demap (and entire MMU
+ * @param type      One of TLB_DEMAP_PAGE and TLB_DEMAP_CONTEXT. Selects
- *          demap on US3).
+ *          between context and page demap.
  * @param context_encoding Specifies which Context register has Context ID for
  *          demap.
  * @param page      Address which is on the page to be demapped.
  */
 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
+{
+    #if 0
+         - this implementation is not correct!!!
+    if (type == TLB_DEMAP_PAGE) {
-    tlb_demap_addr_t da;
+        __hypercall_fast5(
+            MMU_DEMAP_PAGE, 0, 0,
+            page, context_encoding, MMU_FLAG_DTLB);
+    } else if (type == TLB_DEMAP_CONTEXT) {
-    page_address_t pg;
+        __hypercall_fast4(
+            MMU_DEMAP_CTX, 0, 0,
+            context_encoding, MMU_FLAG_DTLB);
+    }
-    da.value = 0;
+    #endif
+}
+/**
-    pg.address = page;
+ * Demaps all mappings in a context.
+ *
-    da.type = type;
+ * @param context   number of the context
+ * @param mmu_flag  MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
+ */
-    da.context = context_encoding;
+static inline void mmu_demap_ctx(int context, int mmu_flag) {
-    da.vpn = pg.vpn;
+    __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
+}
-    /* da.value is the address within the ASI */
+static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
-    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
+    __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
+}
+static inline void mmu_map_perm_addr(uintptr_t vaddr, uintptr_t ra,
+        bool cacheable, bool privileged, bool executable,
+        bool writable, unsigned size, unsigned mmu_flags) {
+    tte_data_t data;
+    data.value = 0;
+    data.v = true;
-    membar();
+    data.ra = ra;
+    data.cp = data.cv = cacheable;
+    data.p = privileged;
+    data.x = executable;
+    data.w = writable;
+    data.size = size;
+    __hypercall_fast4(MMU_MAP_PERM_ADDR, vaddr, 0, data.value, mmu_flags);
+}
-#endif
 extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
-//extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
-//extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 extern void describe_mmu_fault(void);

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(root)//branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tlb.h – Rev 3835 → 3862