WebSVN – HelenOS – Diff – //branches/sparc/kernel/arch/ia64/include/asm.h



 
#include <config.h>
#include <arch/types.h>
#include <arch/register.h>
 
typedef uint64_t ioport_t;
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void  outb(ioport_t port,uint8_t v)
{
    *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void  outw(ioport_t port,uint16_t v)
{
    *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void  outl(ioport_t port,uint32_t v)
{
    *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
 
 
static inline uint8_t inb(ioport_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
}
 
static inline uint16_t inw(ioport_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 ))));
}
 
static inline uint32_t inl(ioport_t port)
{
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
}

 */
static inline uintptr_t get_stack_base(void)
{
    uint64_t v;
 
    //I'm not sure why but this code bad inlines in scheduler, 
    //so THE shifts about 16B and causes kernel panic
    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    //return v;
   
    //this code have the same meaning but inlines well
    asm volatile ("mov %0 = r12" : "=r" (v)  );
    return v & (~(STACK_SIZE-1));
}
 
/** Return Processor State Register.
 *
 * @return PSR.

    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
   
    return v;
}
 
static inline uint64_t cr64_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr64\n" : "=r" (v));
   
    return v;
}
 
 
/** Write ITC (Interval Timer Counter) register.
 *
 * @param v New counter value.
 */
static inline void itc_write(uint64_t v)

Rev 3492	Rev 3593
Line 37...	Line 37...
37		37
38	#include <config.h>	38	#include <config.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <arch/register.h>	40	#include <arch/register.h>
41		41
-		42	typedef uint64_t ioport_t;
42		43
43	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL	44	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
44		45
45	static inline void outb(uint64_t port,uint8_t v)	46	static inline void outb(ioport_t port,uint8_t v)
46	{	47	{
47	((uint8_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	48	((uint8_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;
48		49
49	asm volatile ("mf\n" ::: "memory");	50	asm volatile ("mf\n" ::: "memory");
50	}	51	}
51		52
52	static inline void outw(uint64_t port,uint16_t v)	53	static inline void outw(ioport_t port,uint16_t v)
53	{	54	{
54	((uint16_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	55	((uint16_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;
55		56
56	asm volatile ("mf\n" ::: "memory");	57	asm volatile ("mf\n" ::: "memory");
57	}	58	}
58		59
59	static inline void outl(uint64_t port,uint32_t v)	60	static inline void outl(ioport_t port,uint32_t v)
60	{	61	{
61	((uint32_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;	62	((uint32_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 )))) = v;
62		63
63	asm volatile ("mf\n" ::: "memory");	64	asm volatile ("mf\n" ::: "memory");
64	}	65	}
65		66
66		67
67		68
68	static inline uint8_t inb(uint64_t port)	69	static inline uint8_t inb(ioport_t port)
69	{	70	{
70	asm volatile ("mf\n" ::: "memory");	71	asm volatile ("mf\n" ::: "memory");
71		72
72	return ((uint8_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));	73	return ((uint8_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));
73	}	74	}
74		75
75	static inline uint16_t inw(uint64_t port)	76	static inline uint16_t inw(ioport_t port)
76	{	77	{
77	asm volatile ("mf\n" ::: "memory");	78	asm volatile ("mf\n" ::: "memory");
78		79
79	return ((uint16_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) \| ( (port >> 2) << 12 ))));	80	return ((uint16_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) \| ( (port >> 2) << 12 ))));
80	}	81	}
81		82
82	static inline uint32_t inl(uint64_t port)	83	static inline uint32_t inl(ioport_t port)
83	{	84	{
84	asm volatile ("mf\n" ::: "memory");	85	asm volatile ("mf\n" ::: "memory");
85		86
86	return ((uint32_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));	87	return ((uint32_t )(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) \| ( (port >> 2) << 12 ))));
87	}	88	}
Line 96...	Line 97...
96	*/	97	*/
97	static inline uintptr_t get_stack_base(void)	98	static inline uintptr_t get_stack_base(void)
98	{	99	{
99	uint64_t v;	100	uint64_t v;
100		101
-		102	//I'm not sure why but this code bad inlines in scheduler,
-		103	//so THE shifts about 16B and causes kernel panic
101	asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));	104	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
-		105	//return v;
102		106
-		107	//this code have the same meaning but inlines well
-		108	asm volatile ("mov %0 = r12" : "=r" (v) );
103	return v;	109	return v & (~(STACK_SIZE-1));
104	}	110	}
105		111
106	/** Return Processor State Register.	112	/** Return Processor State Register.
107	*	113	*
108	* @return PSR.	114	* @return PSR.
Line 150...	Line 156...
150	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));	156	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
151		157
152	return v;	158	return v;
153	}	159	}
154		160
-		161	static inline uint64_t cr64_read(void)
-		162	{
-		163	uint64_t v;
-		164
-		165	asm volatile ("mov %0 = cr64\n" : "=r" (v));
-		166
-		167	return v;
-		168	}
-		169
-		170
155	/** Write ITC (Interval Timer Counter) register.	171	/** Write ITC (Interval Timer Counter) register.
156	*	172	*
157	* @param v New counter value.	173	* @param v New counter value.
158	*/	174	*/
159	static inline void itc_write(uint64_t v)	175	static inline void itc_write(uint64_t v)

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(root)//branches/sparc/kernel/arch/ia64/include/asm.h – Rev 3492 → 3593