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53 | */ |
53 | */ |
54 | static inline uintptr_t get_stack_base(void) |
54 | static inline uintptr_t get_stack_base(void) |
55 | { |
55 | { |
56 | uintptr_t v; |
56 | uintptr_t v; |
57 | 57 | ||
- | 58 | asm volatile ( |
|
- | 59 | "and %0, $29, %1\n" |
|
- | 60 | : "=r" (v) |
|
58 | asm volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
61 | : "r" (~(STACK_SIZE-1)) |
- | 62 | ); |
|
59 | 63 | ||
60 | return v; |
64 | return v; |
61 | } |
65 | } |
62 | 66 | ||
63 | extern void cpu_halt(void); |
67 | extern void cpu_halt(void); |
64 | extern void asm_delay_loop(uint32_t t); |
68 | extern void asm_delay_loop(uint32_t t); |
65 | extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
69 | extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
66 | uintptr_t entry); |
70 | uintptr_t entry); |
67 | 71 | ||
68 | extern ipl_t interrupts_disable(void); |
72 | extern ipl_t interrupts_disable(void); |
69 | extern ipl_t interrupts_enable(void); |
73 | extern ipl_t interrupts_enable(void); |
70 | extern void interrupts_restore(ipl_t ipl); |
74 | extern void interrupts_restore(ipl_t ipl); |
71 | extern ipl_t interrupts_read(void); |
75 | extern ipl_t interrupts_read(void); |
- | 76 | extern void asm_delay_loop(uint32_t t); |
|
72 | 77 | ||
73 | /** No I/O port address space on MIPS. */ |
- | |
74 | static inline void outb(ioport_t port, uint8_t v) |
78 | static inline void pio_write_8(ioport_t port, uint8_t v) |
75 | { |
79 | { |
- | 80 | /* XXX */ |
|
76 | } |
81 | } |
77 | 82 | ||
78 | /** No I/O port address space on MIPS. */ |
- | |
79 | static inline uint8_t inb(ioport_t port) |
83 | static inline uint8_t pio_read_8(ioport_t port) |
80 | { |
84 | { |
81 | return 0; |
85 | return 0; /* XXX */ |
82 | } |
86 | } |
83 | 87 | ||
84 | #endif |
88 | #endif |
85 | 89 | ||
86 | /** @} |
90 | /** @} |