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Rev 2927 Rev 3191
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <preemption.h>
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#include <preemption.h>
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static inline void atomic_inc(atomic_t *val) {
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static inline void atomic_inc(atomic_t *val) {
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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    asm volatile ("lock incl %0\n" : "=m" (val->count));
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    asm volatile ("lock incl %0\n" : "+m" (val->count));
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#else
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#else
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    asm volatile ("incl %0\n" : "=m" (val->count));
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    asm volatile ("incl %0\n" : "+m" (val->count));
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_SMP */
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}
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}
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static inline void atomic_dec(atomic_t *val) {
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static inline void atomic_dec(atomic_t *val) {
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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    asm volatile ("lock decl %0\n" : "=m" (val->count));
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    asm volatile ("lock decl %0\n" : "+m" (val->count));
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#else
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#else
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    asm volatile ("decl %0\n" : "=m" (val->count));
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    asm volatile ("decl %0\n" : "+m" (val->count));
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_SMP */
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}
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}
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static inline long atomic_postinc(atomic_t *val)
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static inline long atomic_postinc(atomic_t *val)
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{
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{
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    long r = 1;
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    long r = 1;
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    asm volatile (
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    asm volatile (
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        "lock xaddl %1, %0\n"
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        "lock xaddl %1, %0\n"
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        : "=m" (val->count), "+r" (r)
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        : "+m" (val->count), "+r" (r)
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    );
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    );
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    return r;
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    return r;
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}
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}
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{
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{
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    long r = -1;
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    long r = -1;
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    asm volatile (
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    asm volatile (
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        "lock xaddl %1, %0\n"
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        "lock xaddl %1, %0\n"
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        : "=m" (val->count), "+r"(r)
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        : "+m" (val->count), "+r"(r)
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    );
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    );
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    return r;
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    return r;
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}
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}
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#define atomic_preinc(val) (atomic_postinc(val)+1)
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#define atomic_preinc(val) (atomic_postinc(val) + 1)
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#define atomic_predec(val) (atomic_postdec(val)-1)
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#define atomic_predec(val) (atomic_postdec(val) - 1)
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static inline uint32_t test_and_set(atomic_t *val) {
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static inline uint32_t test_and_set(atomic_t *val) {
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    uint32_t v;
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    uint32_t v;
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    asm volatile (
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    asm volatile (
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        "movl $1, %0\n"
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        "movl $1, %0\n"
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        "xchgl %0, %1\n"
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        "xchgl %0, %1\n"
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        : "=r" (v),"=m" (val->count)
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        : "=r" (v),"+m" (val->count)
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    );
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    );
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    return v;
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    return v;
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}
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}
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{
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{
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    uint32_t tmp;
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    uint32_t tmp;
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    preemption_disable();
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    preemption_disable();
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    asm volatile (
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    asm volatile (
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        "0:;"
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        "0:\n"
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#ifdef CONFIG_HT
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#ifdef CONFIG_HT
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        "pause;" /* Pentium 4's HT love this instruction */
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        "pause\n" /* Pentium 4's HT love this instruction */
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#endif
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#endif
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        "mov %0, %1;"
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        "mov %0, %1\n"
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        "testl %1, %1;"
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        "testl %1, %1\n"
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        "jnz 0b;"       /* Lightweight looping on locked spinlock */
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        "jnz 0b\n"       /* lightweight looping on locked spinlock */
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        "incl %1;"      /* now use the atomic operation */
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        "incl %1\n"      /* now use the atomic operation */
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        "xchgl %0, %1;"
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        "xchgl %0, %1\n"   
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        "testl %1, %1;"
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        "testl %1, %1\n"
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        "jnz 0b;"
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        "jnz 0b\n"
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                : "=m"(val->count),"=r"(tmp)
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                : "+m" (val->count), "=r"(tmp)
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        );
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    );
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    /*
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    /*
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     * Prevent critical section code from bleeding out this way up.
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     * Prevent critical section code from bleeding out this way up.
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     */
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     */
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    CS_ENTER_BARRIER();
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    CS_ENTER_BARRIER();
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}
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}