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34 | 34 | ||
35 | #ifndef LIBC_ia32_ATOMIC_H_ |
35 | #ifndef LIBC_ia32_ATOMIC_H_ |
36 | #define LIBC_ia32_ATOMIC_H_ |
36 | #define LIBC_ia32_ATOMIC_H_ |
37 | 37 | ||
38 | static inline void atomic_inc(atomic_t *val) { |
38 | static inline void atomic_inc(atomic_t *val) { |
39 | asm volatile ("lock incl %0\n" : "=m" (val->count)); |
39 | asm volatile ("lock incl %0\n" : "+m" (val->count)); |
40 | } |
40 | } |
41 | 41 | ||
42 | static inline void atomic_dec(atomic_t *val) { |
42 | static inline void atomic_dec(atomic_t *val) { |
43 | asm volatile ("lock decl %0\n" : "=m" (val->count)); |
43 | asm volatile ("lock decl %0\n" : "+m" (val->count)); |
44 | } |
44 | } |
45 | 45 | ||
46 | static inline long atomic_postinc(atomic_t *val) |
46 | static inline long atomic_postinc(atomic_t *val) |
47 | { |
47 | { |
48 | long r; |
48 | long r; |
49 | 49 | ||
50 | asm volatile ( |
50 | asm volatile ( |
51 | "movl $1, %0\n" |
51 | "movl $1, %0\n" |
52 | "lock xaddl %0, %1\n" |
52 | "lock xaddl %0, %1\n" |
53 | : "=r" (r), "=m" (val->count) |
53 | : "=r" (r), "+m" (val->count) |
54 | ); |
54 | ); |
55 | 55 | ||
56 | return r; |
56 | return r; |
57 | } |
57 | } |
58 | 58 | ||
Line 61... | Line 61... | ||
61 | long r; |
61 | long r; |
62 | 62 | ||
63 | asm volatile ( |
63 | asm volatile ( |
64 | "movl $-1, %0\n" |
64 | "movl $-1, %0\n" |
65 | "lock xaddl %0, %1\n" |
65 | "lock xaddl %0, %1\n" |
66 | : "=r" (r), "=m" (val->count) |
66 | : "=r" (r), "+m" (val->count) |
67 | ); |
67 | ); |
68 | 68 | ||
69 | return r; |
69 | return r; |
70 | } |
70 | } |
71 | 71 | ||
72 | #define atomic_preinc(val) (atomic_postinc(val)+1) |
72 | #define atomic_preinc(val) (atomic_postinc(val) + 1) |
73 | #define atomic_predec(val) (atomic_postdec(val)-1) |
73 | #define atomic_predec(val) (atomic_postdec(val) - 1) |
74 | 74 | ||
75 | #endif |
75 | #endif |
76 | 76 | ||
77 | /** @} |
77 | /** @} |
78 | */ |
78 | */ |