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Rev 3022 | Rev 4296 | ||
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Line 101... | Line 101... | ||
101 | * this treatment. |
101 | * this treatment. |
102 | * |
102 | * |
103 | * Note that branch-delay slots are used in order to save space. |
103 | * Note that branch-delay slots are used in order to save space. |
104 | */ |
104 | */ |
105 | 0: |
105 | 0: |
- | 106 | sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 |
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106 | mov VA_DMMU_TAG_ACCESS, %g1 |
107 | wr %g0, ASI_DMMU, %asi |
107 | ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
108 | ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN |
108 | set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
109 | set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
109 | andcc %g1, %g2, %g3 ! get Context |
110 | andcc %g1, %g2, %g3 ! get Context |
110 | bnz 0f ! Context is non-zero |
111 | bnz %xcc, 0f ! Context is non-zero |
111 | andncc %g1, %g2, %g3 ! get page address into %g3 |
112 | andncc %g1, %g2, %g3 ! get page address into %g3 |
112 | bz 0f ! page address is zero |
113 | bz %xcc, 0f ! page address is zero |
- | 114 | ldx [%g7 + %lo(end_of_identity)], %g4 |
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- | 115 | cmp %g3, %g4 |
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- | 116 | bgeu %xcc, 0f |
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113 | 117 | ||
114 | sethi %hi(kernel_8k_tlb_data_template), %g2 |
- | |
115 | ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2 |
118 | ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 |
116 | or %g3, %g2, %g2 |
119 | add %g3, %g2, %g2 |
117 | stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
120 | stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
118 | retry |
121 | retry |
119 | 122 | ||
120 | /* |
123 | /* |
121 | * Third, catch and handle special cases when the trap is caused by |
124 | * Third, catch and handle special cases when the trap is caused by |
Line 136... | Line 139... | ||
136 | 139 | ||
137 | /* |
140 | /* |
138 | * Read the Tag Access register for the higher-level handler. |
141 | * Read the Tag Access register for the higher-level handler. |
139 | * This is necessary to survive nested DTLB misses. |
142 | * This is necessary to survive nested DTLB misses. |
140 | */ |
143 | */ |
141 | mov VA_DMMU_TAG_ACCESS, %g2 |
144 | ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2 |
142 | ldxa [%g2] ASI_DMMU, %g2 |
- | |
143 | 145 | ||
144 | /* |
146 | /* |
145 | * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
147 | * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
146 | */ |
148 | */ |
147 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
149 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |