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38 | #define CR_IVR_MASK 0xf |
38 | #define CR_IVR_MASK 0xf |
39 | #define PSR_IC_MASK 0x2000 |
39 | #define PSR_IC_MASK 0x2000 |
40 | #define PSR_I_MASK 0x4000 |
40 | #define PSR_I_MASK 0x4000 |
41 | #define PSR_PK_MASK 0x8000 |
41 | #define PSR_PK_MASK 0x8000 |
42 | 42 | ||
43 | #define PSR_DT_MASK (1<<17) |
43 | #define PSR_DT_MASK (1 << 17) |
44 | #define PSR_RT_MASK (1<<27) |
44 | #define PSR_RT_MASK (1 << 27) |
45 | 45 | ||
46 | #define PSR_DFL_MASK (1<<18) |
46 | #define PSR_DFL_MASK (1 << 18) |
47 | #define PSR_DFH_MASK (1<<19) |
47 | #define PSR_DFH_MASK (1 << 19) |
48 | 48 | ||
49 | #define PSR_IT_MASK 0x0000001000000000 |
49 | #define PSR_IT_MASK 0x0000001000000000 |
50 | 50 | ||
51 | #define PSR_CPL_SHIFT 32 |
51 | #define PSR_CPL_SHIFT 32 |
52 | #define PSR_CPL_MASK_SHIFTED 3 |
52 | #define PSR_CPL_MASK_SHIFTED 3 |