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| Rev 3022 | Rev 4055 | ||
|---|---|---|---|
| Line 72... | Line 72... | ||
| 72 | static inline uint32_t has_cpuid(void) |
72 | static inline uint32_t has_cpuid(void) |
| 73 | { |
73 | { |
| 74 | uint32_t val, ret; |
74 | uint32_t val, ret; |
| 75 | 75 | ||
| 76 | asm volatile ( |
76 | asm volatile ( |
| 77 | "pushf\n" /* read flags */ |
77 | "pushf\n" /* read flags */ |
| 78 | "popl %0\n" |
78 | "popl %[ret]\n" |
| 79 | "movl %0, %1\n" |
79 | "movl %[ret], %[val]\n" |
| 80 | 80 | ||
| 81 | "btcl $21, %1\n" /* swap the ID bit */ |
81 | "btcl $21, %[val]\n" /* swap the ID bit */ |
| 82 | 82 | ||
| 83 | "pushl %1\n" /* propagate the change into flags */ |
83 | "pushl %[val]\n" /* propagate the change into flags */ |
| 84 | "popf\n" |
84 | "popf\n" |
| 85 | "pushf\n" |
85 | "pushf\n" |
| 86 | "popl %1\n" |
86 | "popl %[val]\n" |
| 87 | 87 | ||
| 88 | "andl $(1 << 21), %0\n" /* interrested only in ID bit */ |
88 | "andl $(1 << 21), %[ret]\n" /* interrested only in ID bit */ |
| 89 | "andl $(1 << 21), %1\n" |
89 | "andl $(1 << 21), %[val]\n" |
| 90 | "xorl %1, %0\n" |
90 | "xorl %[val], %[ret]\n" |
| 91 | : "=r" (ret), "=r" (val) |
91 | : [ret] "=r" (ret), [val] "=r" (val) |
| 92 | ); |
92 | ); |
| 93 | 93 | ||
| 94 | return ret; |
94 | return ret; |
| 95 | } |
95 | } |
| 96 | 96 | ||
| 97 | static inline void cpuid(uint32_t cmd, cpu_info_t *info) |
97 | static inline void cpuid(uint32_t cmd, cpu_info_t *info) |
| 98 | { |
98 | { |
| 99 | asm volatile ( |
99 | asm volatile ( |
| 100 | "cpuid\n" |
100 | "cpuid\n" |
| 101 | : "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx), "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx) |
101 | : "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx), |
| - | 102 | "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx) |
|
| 102 | : "a" (cmd) |
103 | : "a" (cmd) |
| 103 | ); |
104 | ); |
| 104 | } |
105 | } |
| 105 | 106 | ||
| 106 | #endif |
107 | #endif |