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Rev 3022 | Rev 4055 | ||
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Line 153... | Line 153... | ||
153 | d->offset_32_63 = offset >> 32; |
153 | d->offset_32_63 = offset >> 32; |
154 | } |
154 | } |
155 | 155 | ||
156 | void tss_initialize(tss_t *t) |
156 | void tss_initialize(tss_t *t) |
157 | { |
157 | { |
158 | memsetb((uintptr_t) t, sizeof(tss_t), 0); |
158 | memsetb(t, sizeof(tss_t), 0); |
159 | } |
159 | } |
160 | 160 | ||
161 | /* |
161 | /* |
162 | * This function takes care of proper setup of IDT and IDTR. |
162 | * This function takes care of proper setup of IDT and IDTR. |
163 | */ |
163 | */ |
Line 207... | Line 207... | ||
207 | * ahead of page_init */ |
207 | * ahead of page_init */ |
208 | write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); |
208 | write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); |
209 | 209 | ||
210 | tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
210 | tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
211 | if (!tss_p) |
211 | if (!tss_p) |
212 | panic("could not allocate TSS\n"); |
212 | panic("Cannot allocate TSS."); |
213 | } |
213 | } |
214 | 214 | ||
215 | tss_initialize(tss_p); |
215 | tss_initialize(tss_p); |
216 | 216 | ||
217 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); |
217 | tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); |
Line 237... | Line 237... | ||
237 | void arch_reboot(void) |
237 | void arch_reboot(void) |
238 | { |
238 | { |
239 | preemption_disable(); |
239 | preemption_disable(); |
240 | ipl_t ipl = interrupts_disable(); |
240 | ipl_t ipl = interrupts_disable(); |
241 | 241 | ||
242 | memsetb((uintptr_t) idt, sizeof(idt), 0); |
242 | memsetb(idt, sizeof(idt), 0); |
243 | idtr_load(&idtr); |
243 | idtr_load(&idtr); |
244 | 244 | ||
245 | interrupts_restore(ipl); |
245 | interrupts_restore(ipl); |
246 | asm volatile ( |
246 | asm volatile ( |
247 | "int $0x03\n" |
247 | "int $0x03\n" |