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Rev 3022 | Rev 4055 | ||
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Line 28... | Line 28... | ||
28 | # |
28 | # |
29 | 29 | ||
30 | #include <stack.h> |
30 | #include <stack.h> |
31 | #include <register.h> |
31 | #include <register.h> |
32 | 32 | ||
- | 33 | .register %g2, #scratch |
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- | 34 | .register %g3, #scratch |
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- | 35 | ||
33 | .text |
36 | .text |
34 | 37 | ||
35 | .global halt |
38 | .global halt |
36 | .global memcpy |
39 | .global memcpy |
37 | .global jump_to_kernel |
40 | .global jump_to_kernel |
Line 39... | Line 42... | ||
39 | halt: |
42 | halt: |
40 | b halt |
43 | b halt |
41 | nop |
44 | nop |
42 | 45 | ||
43 | memcpy: |
46 | memcpy: |
44 | .register %g2, #scratch |
47 | mov %o0, %o3 ! save dst |
45 | .register %g3, #scratch |
- | |
46 | add %o1, 7, %g1 |
48 | add %o1, 7, %g1 |
47 | and %g1, -8, %g1 |
49 | and %g1, -8, %g1 |
48 | cmp %o1, %g1 |
50 | cmp %o1, %g1 |
49 | be,pn %xcc, 3f |
51 | be,pn %xcc, 3f |
50 | add %o0, 7, %g1 |
52 | add %o0, 7, %g1 |
Line 59... | Line 61... | ||
59 | stb %g1, [%g3 + %o0] |
61 | stb %g1, [%g3 + %o0] |
60 | bne,pt %xcc, 1b |
62 | bne,pt %xcc, 1b |
61 | mov %g2, %g3 |
63 | mov %g2, %g3 |
62 | 2: |
64 | 2: |
63 | jmp %o7 + 8 ! exit point |
65 | jmp %o7 + 8 ! exit point |
64 | mov %o1, %o0 |
66 | mov %o3, %o0 |
65 | 3: |
67 | 3: |
66 | and %g1, -8, %g1 |
68 | and %g1, -8, %g1 |
67 | cmp %o0, %g1 |
69 | cmp %o0, %g1 |
68 | bne,pt %xcc, 0b |
70 | bne,pt %xcc, 0b |
69 | mov 0, %g3 |
71 | mov 0, %g3 |
Line 93... | Line 95... | ||
93 | cmp %o2, %g2 |
95 | cmp %o2, %g2 |
94 | bne,pt %xcc, 6b |
96 | bne,pt %xcc, 6b |
95 | mov %g2, %g3 |
97 | mov %g2, %g3 |
96 | 98 | ||
97 | jmp %o7 + 8 ! exit point |
99 | jmp %o7 + 8 ! exit point |
98 | mov %o1, %o0 |
100 | mov %o3, %o0 |
99 | 101 | ||
100 | jump_to_kernel: |
102 | jump_to_kernel: |
- | 103 | /* |
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- | 104 | * We have copied code and now we need to guarantee cache coherence. |
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- | 105 | * 1. Make sure that the code we have moved has drained to main memory. |
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- | 106 | * 2. Invalidate I-cache. |
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- | 107 | * 3. Flush instruction pipeline. |
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- | 108 | */ |
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- | 109 | ||
- | 110 | /* |
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- | 111 | * US3 processors have a write-invalidate cache, so explicitly |
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- | 112 | * invalidating it is not required. Whether to invalidate I-cache |
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- | 113 | * or not is decided according to the value of the global |
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- | 114 | * "subarchitecture" variable (set in the bootstrap). |
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- | 115 | */ |
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- | 116 | set subarchitecture, %g2 |
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- | 117 | ldub [%g2], %g2 |
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- | 118 | cmp %g2, 3 |
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- | 119 | be 1f |
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- | 120 | nop |
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- | 121 | 0: |
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- | 122 | call icache_flush |
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- | 123 | nop |
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- | 124 | 1: |
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- | 125 | membar #StoreStore |
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- | 126 | ||
- | 127 | /* |
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- | 128 | * Flush the instruction pipeline. |
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- | 129 | */ |
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- | 130 | flush %i7 |
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- | 131 | ||
101 | mov %o0, %l1 |
132 | mov %o0, %l1 |
102 | mov %o1, %o0 |
133 | mov %o1, %o0 |
103 | mov %o2, %o1 |
134 | mov %o2, %o1 |
104 | mov %o3, %o2 |
135 | mov %o3, %o2 |
105 | jmp %l1 ! jump to kernel |
136 | jmp %l1 ! jump to kernel |
106 | nop |
137 | nop |
107 | 138 | ||
- | 139 | #define ICACHE_SIZE 8192 |
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- | 140 | #define ICACHE_LINE_SIZE 32 |
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- | 141 | #define ICACHE_SET_BIT (1 << 13) |
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- | 142 | #define ASI_ICACHE_TAG 0x67 |
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- | 143 | ||
- | 144 | # Flush I-cache |
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- | 145 | icache_flush: |
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- | 146 | set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 |
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- | 147 | stxa %g0, [%g1] ASI_ICACHE_TAG |
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- | 148 | 0: membar #Sync |
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- | 149 | subcc %g1, ICACHE_LINE_SIZE, %g1 |
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- | 150 | bnz,pt %xcc, 0b |
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- | 151 | stxa %g0, [%g1] ASI_ICACHE_TAG |
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- | 152 | membar #Sync |
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- | 153 | retl |
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- | 154 | ! SF Erratum #51 |
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- | 155 | nop |
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108 | .global ofw |
156 | .global ofw |
109 | ofw: |
157 | ofw: |
110 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
158 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
111 | set ofw_cif, %l0 |
159 | set ofw_cif, %l0 |
112 | ldx [%l0], %l0 |
160 | ldx [%l0], %l0 |