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Rev 3022 Rev 4055
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include "regname.h"
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#include "regname.h"
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#define INITIAL_STACK 0x80040000
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#include "main.h"
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.set noat
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.set noat
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.set noreorder
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.set noreorder
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.set nomacro
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.set nomacro
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.section BOOTSTRAP
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.section BOOTSTRAP
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.global start
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.global start
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start:
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start:
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	lui $sp, INITIAL_STACK >> 16
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	ori $sp, $sp, INITIAL_STACK & 0xffff
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	/* Setup CPU map (on msim this code
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	   is executed in parallel on all CPUs,
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	   but it not an issue) */
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	la $a0, CPUMAP
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	sw $zero, 0($a0)
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	sw $zero, 4($a0)
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	j bootstrap
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	sw $zero, 8($a0)
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	sw $zero, 12($a0)
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	sw $zero, 16($a0)
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	sw $zero, 20($a0)
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	sw $zero, 24($a0)
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	sw $zero, 28($a0)
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	sw $zero, 32($a0)
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	sw $zero, 36($a0)
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	sw $zero, 40($a0)
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	sw $zero, 44($a0)
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	sw $zero, 48($a0)
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	sw $zero, 52($a0)
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	sw $zero, 56($a0)
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	sw $zero, 60($a0)
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	sw $zero, 64($a0)
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	sw $zero, 68($a0)
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	sw $zero, 72($a0)
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	sw $zero, 76($a0)
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	sw $zero, 80($a0)
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	sw $zero, 84($a0)
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	sw $zero, 88($a0)
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	sw $zero, 92($a0)
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	sw $zero, 96($a0)
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	sw $zero, 100($a0)
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	sw $zero, 104($a0)
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	sw $zero, 108($a0)
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	sw $zero, 112($a0)
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	sw $zero, 116($a0)
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	sw $zero, 120($a0)
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	sw $zero, 124($a0)
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	lui $a1, 1
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#ifdef MACHINE_msim
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	/* Read dorder value */
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	la $k0, MSIM_DORDER_ADDRESS
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	lw $k1, ($k0)
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	/* If we are not running on BSP
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	   then end in an infinite loop  */
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	beq $k1, $zero, bsp
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	nop
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	nop
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	/* Record CPU presence */
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	sll $a2, $k1, 2
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	addu $a2, $a2, $a0
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	sw $a1, ($a2)
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	loop:
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		j loop
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		nop
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#endif
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	bsp:
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		/* Record CPU presence */
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		sw $a1, ($a0)
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		/* Setup initial stack */
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		la $sp, INITIAL_STACK
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		j bootstrap
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		nop