WebSVN – HelenOS – Diff – //branches/arm/kernel/arch/arm32/src/mm/page_fault.c

 #include <genarch/mm/page_pt.h>
 #include <arch.h>
 #include <interrupt.h>
-//TODO: remove in final version
-static void print_istate(istate_t* istate);
+/** Returns value stored in fault status register.
-static void print_istate(istate_t* istate) {
-    dprintf("\nIstate dump:\n");
-    dprintf("    r0:%X    r1:%X    r2:%X    r3:%X\n", istate->r0,  istate->r1, istate->r2,  istate->r3);
-    dprintf("    r4:%X    r5:%X    r6:%X    r7:%X\n", istate->r4,  istate->r5, istate->r6,  istate->r7);
-    dprintf("    r8:%X    r8:%X   r10:%X   r11:%X\n", istate->r8,  istate->r9, istate->r10, istate->r11);
-    dprintf("   r12:%X    sp:%X    lr:%X  spsr:%X\n", istate->r12, istate->sp, istate->lr,  istate->spsr);
-    dprintf("   pc:%X\n", istate->pc);
+ *
-}
-/**
- * \return Value stored in fault status register
+ *  \return Value stored in CP15 fault status register (FSR).
  */
-static inline fault_status_t read_fault_status_register() {
+static inline fault_status_t read_fault_status_register(void)
+{
-        fault_status_union_t tmp;
+    fault_status_union_t fsu;
+    // fault adress is stored in CP15 register 5
-        asm volatile (
+    asm volatile (
         "mrc p15, 0, %0, c5, c0, 0"
-            : "=r"(tmp.dummy)
+        : "=r"(fsu.dummy)
     );
-    return tmp.fsr;
+    return fsu.fs;
+}
+/** Returns FAR (fault address register) content.
-/**
+ *
- * \return Virtual adress. Access on this addres caused exception
+ *  \return FAR (fault address register) content (address that caused a page fault)
  */
-static inline uintptr_t read_fault_address_register() {
+static inline uintptr_t read_fault_address_register(void)
+{
-        uintptr_t tmp;
+    uintptr_t ret;
-    // Fault adress is stored in coprocessor15, register 6
+    // fault adress is stored in CP15 register 6
     asm volatile (
         "mrc p15, 0, %0, c6, c0, 0"
-        : "=r"(tmp)
+        : "=r"(ret)
     );
-    return tmp;
+    return ret;
-};
+}
-/** Check type of instruction
- * \param i_code Instruction op code
- * \return true if instruction is load or store, false otherwise
- */
-static inline bool load_store_instruction(instruction_t i_code) {
+/** Decides whether the instructions is load/store or not.
+ *
+ * \param instr Instruction
+ *
+ * \return true when instruction is load/store, false otherwise
+ */
+static inline bool is_load_store_instruction(instruction_t instr)
+{
-     // load store immediate offset
+    // load store immediate offset
-    if (i_code.instr_type == 0x2) {
+    if (instr.type == 0x2) {
         return true;
-    };
+    }
-        // load store register offset
+    // load store register offset
-        if (i_code.instr_type == 0x3 && i_code.bit4 == 0) {
+    if (instr.type == 0x3 && instr.bit4 == 0) {
         return true;
-    };
+    }
-        // load store multiple
+    // load store multiple
-        if (i_code.instr_type == 0x4) {
+    if (instr.type == 0x4) {
         return true;
-    };
+    }
-        // coprocessor load / strore
+    // coprocessor load/store
-    if (i_code.instr_type == 0x6) {
+    if (instr.type == 0x6) {
         return true;
-    };
+    }
     return false;
+}
-/** Check type of instruction
- * \param i_code Instruction op code
- * \return true if instruction is swap, false otherwise
- */
-static inline bool swap_instruction(instruction_t i_code) {
+/** Decides whether the instructions is swap or not.
+ *
+ * \param instr Instruction
+ *
+ * \return true when instruction is swap, false otherwise
+ */
+static inline bool is_swap_instruction(instruction_t instr)
+{
     // swap, swapb instruction
-    if (i_code.instr_type == 0x0 &&
+    if (instr.type == 0x0 &&
-        (i_code.opcode == 0x8 || i_code.opcode == 0xA) &&
+        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
-        i_code.access == 0x0 && i_code.bits567 == 0x4 &&
+        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
-        i_code.bit4 == 1) {
         return true;
-    };
+    }
     return false;
+}
-/**
- * Decode instruction and decide if try to read or write into memmory.
+/** Decides whether read or write into memory is requested.
+ *
- * \param instr_addr address of instruction which attempts access into memmory
+ * \param instr_addr   Address of instruction which tries to access memory
- * \param badvaddr Virtual address on which instruction tries to access
+ * \param badvaddr     Virtual address the instruction tries to access
+ *
- * \return type of access into memmory
+ * \return Type of access into memmory
- *  Note: return PF_ACESS_EXEC if no memmory acess
+ * \note   Returns #PF_ACESS_EXEC if no memory access is requested
  */
 //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC
-static pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr) {
+static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)
+{
-        instruction_union_t tmp;
+    instruction_union_t instr_union;
-        tmp.ip = instr_addr;
+    instr_union.pc = instr_addr;
-    // get instruction op code
-    instruction_t i_code = *(tmp.instr);
-//         dprintf("get_instruction_memmory_access\n");
-//  dprintf(" instr_addr:%X\n",instr_addr);
-//  dprintf(" i_code:%X\n",i_code);
-//  dprintf(" i_code.condition:%d\n", i_code.condition);
-//  dprintf(" i_code.instr_type:%d\n",i_code.instr_type);
+    instruction_t instr = *(instr_union.instr);
-//  dprintf(" i_code.opcode:%d\n",i_code.opcode);
-//  dprintf(" i_code.acess:%d\n", i_code.access);
-//  dprintf(" i_code.dummy:%d\n", i_code.dummy);
-//  dprintf(" i_code.bits567%d\n", i_code.bits567);
-//  dprintf(" i_code.bit4:%d\n", i_code.bit4);
-//  dprintf(" i_code.dummy1:%d\n", i_code.dummy1);
-        // undefined instructions ... (or special instructions)
+    // undefined instructions
-    if (i_code.condition == 0xf) {
+    if (instr.condition == 0xf) {
-        panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr);
+        panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)",
+            instr, badvaddr);
         return PF_ACCESS_EXEC;
-    };
+    }
     // load store instructions
-        if (load_store_instruction(i_code)) {
+    if (is_load_store_instruction(instr)) {
-        if ( i_code.access == 1) {
+        if (instr.access == 1) {
             return PF_ACCESS_READ;
         } else {
             return PF_ACCESS_WRITE;
+        }
-    };
+    }
     // swap, swpb instruction
-    if (swap_instruction(i_code))
+    if (is_swap_instruction(instr)) {
-     {
         /* Swap instructions make read and write in one step.
          * Type of access that caused exception have to page tables
          *  and access rights.
          */
-//TODO: ALF!!!!! cann't use AS as is define as THE->as and THE structure is sored after stack_base of current thread
+        //TODO: ALF!!!!! cann't use AS asi is define as THE->as and THE structure is
+        //sored after stack_base of current thread
-//      but now ... in exception we have separate stacks <==> different stack_pointer ... so AS contains nonsence data
+        //but now ... in exception we have separate stacks <==> different
+        //stack_pointer ... so AS contains nonsence data
-//  same case as_page_fault .... it's nessesary to solve "stack" problem
+        //same case as_page_fault .... it's nessesary to solve "stack" problem
-                pte_level1_t* pte = (pte_level1_t*)
+        pte_level1_t* pte = (pte_level1_t*)
-            pt_mapping_operations.mapping_find(AS, badvaddr);
+        pt_mapping_operations.mapping_find(AS, badvaddr);
         ASSERT(pte);
-                /* check if read possible
+        /* check if read possible
-                 * Note: Don't check PTE_READABLE because it returns 1 everytimes */
+        * Note: Don't check PTE_READABLE because it returns 1 everytimes */
         if ( !PTE_PRESENT(pte) ) {
-                return PF_ACCESS_READ;
+            return PF_ACCESS_READ;
+        }
         if ( !PTE_WRITABLE(pte) ) {
             return PF_ACCESS_WRITE;
-        }
-        else
+        } else {
             // badvaddr is present readable and writeable but error occured ... why?
-            panic("page_fault - swap instruction, but address readable and writeable (instr_code:%X, badvaddr:%X)",i_code, badvaddr);
+            panic("page_fault - swap instruction, but address readable and writeable"
+                "(instr_code:%X, badvaddr:%X)", instr, badvaddr);
+        }
+    }
-    panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr);
-    return PF_ACCESS_EXEC;
-}
-/**
- * Routine that solves exception data_abourt
- *  ... you try to load or store value into invalid memmory address
- * \param istate State of CPU when data abourt occured
- * \param n number of exception
- */
-//TODO: remove debug prints in final tested version
-void data_abort(int n, istate_t *istate) {
-        fault_status_t fsr = read_fault_status_register();
-        uintptr_t  page = read_fault_address_register();
-    pf_access_t access = get_memmory_access_type( istate->pc, page);
-//  print_istate(istate);
-    dprintf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->pc, page, fsr.status,fsr, access);
+    panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)",
-/* Alf: Will be commented until stack problem will be solved ...
-    as_page_fault make consequent page faults*/
-        int ret = as_page_fault(page, access, istate);
-    dprintf(" as_page_fault ret:%d\n", ret);
-        if (ret == AS_PF_FAULT) {
-        fault_if_from_uspace(istate, "Page fault: %#x", page);
-        panic("page fault\n");
+        instr, badvaddr);
-        }
-    // TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures
-//  panic("page fault ... solved\n");
+    return PF_ACCESS_EXEC;
+}
+/** Handles "data abort" exception (load or store at invalid address).
-/**
+ *
- * Routine that solves exception prefetch_about
+ * \param exc_no    exception number
- *  ... you try to execute instruction on invalid address
- * \param istate State of CPU when prefetch abourt occured
+ * \param istate    CPU state when exception occured
- * \param n number of exception
  */
-void prefetch_abort(int n, istate_t *istate) {
+void data_abort(int exc_no, istate_t *istate)
+{
+    fault_status_t fsr = read_fault_status_register();
+    uintptr_t badvaddr = read_fault_address_register();
+    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
+    int ret = as_page_fault(badvaddr, access, istate);
+    if (ret == AS_PF_FAULT) {
-    print_istate(istate);
+        print_istate(istate);
-    dprintf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->pc);
+        dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",
+            istate->pc, badvaddr, fsr.status, fsr, access);
-/* Alf: Will be commented until stack problem will be solved ...
+        fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
-    as_page_fault make consequent page faults*/
+        panic("page fault\n");
+    }
+}
+/** Handles "prefetch abort" exception (instruction couldn't be executed).
+ *
+ * \param exc_no    exception number
+ * \param istate    CPU state when exception occured
+ */
+void prefetch_abort(int exc_no, istate_t *istate)
+{
     int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
-    dprintf(" as_page_fault ret:%d\n", ret);
-        if (ret == AS_PF_FAULT) {
-                panic("page fault - instruction fetch at addr:%X\n", istate->pc);
-        }
+    if (ret == AS_PF_FAULT) {
-//  panic("Prefetch abourt ... solved");
+        dprintf("prefetch_abort\n");
+        print_istate(istate);
+        panic("page fault - prefetch_abort at address: %x\n", istate->pc);
+    }
+}
 /** @}
  */

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(root)//branches/arm/kernel/arch/arm32/src/mm/page_fault.c – Rev 2298 → 2304