Rev 2312 | Rev 2410 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2312 | Rev 2329 | ||
---|---|---|---|
Line 35... | Line 35... | ||
35 | */ |
35 | */ |
36 | 36 | ||
37 | #ifndef KERN_arm32_REGUTILS_H_ |
37 | #ifndef KERN_arm32_REGUTILS_H_ |
38 | #define KERN_arm32_REGUTILS_H_ |
38 | #define KERN_arm32_REGUTILS_H_ |
39 | 39 | ||
40 | #define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
- | |
41 | #define STATUS_REG_MODE_MASK 0x1F |
- | |
42 | 40 | ||
43 | #define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
41 | #define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
- | 42 | #define STATUS_REG_MODE_MASK 0x1f |
|
44 | 43 | ||
- | 44 | #define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
|
45 | 45 | ||
46 | /* ARM Processor Operation Modes */ |
- | |
47 | #define USER_MODE 0x10 |
- | |
48 | #define FIQ_MODE 0x11 |
- | |
49 | #define IRQ_MODE 0x12 |
- | |
50 | #define SUPERVISOR_MODE 0x13 |
- | |
51 | #define ABORT_MODE 0x17 |
- | |
52 | #define UNDEFINED_MODE 0x1b |
- | |
53 | #define SYSTEM_MODE 0x1f |
- | |
54 | 46 | ||
- | 47 | /* ARM Processor Operation Modes */ |
|
- | 48 | #define USER_MODE 0x10 |
|
- | 49 | #define FIQ_MODE 0x11 |
|
- | 50 | #define IRQ_MODE 0x12 |
|
- | 51 | #define SUPERVISOR_MODE 0x13 |
|
- | 52 | #define ABORT_MODE 0x17 |
|
- | 53 | #define UNDEFINED_MODE 0x1b |
|
- | 54 | #define SYSTEM_MODE 0x1f |
|
55 | 55 | ||
56 | 56 | ||
57 | /* [CS]PRS manipulation macros */ |
57 | /* [CS]PRS manipulation macros */ |
58 | #define GEN_STATUS_READ(nm,reg) \ |
58 | #define GEN_STATUS_READ(nm,reg) \ |
59 | static inline uint32_t nm## _status_reg_read(void) \ |
59 | static inline uint32_t nm## _status_reg_read(void) \ |
60 | { \ |
60 | { \ |
61 | uint32_t retval; \ |
61 | uint32_t retval; \ |
62 | asm("mrs %0, " #reg : "=r"(retval)); \ |
62 | asm volatile("mrs %0, " #reg : "=r"(retval)); \ |
63 | return retval; \ |
63 | return retval; \ |
64 | } |
64 | } |
65 | 65 | ||
66 | #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
66 | #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
67 | static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
67 | static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
68 | { \ |
68 | { \ |
69 | asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
69 | asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
70 | } |
70 | } |
71 | 71 | ||
72 | 72 | ||
73 | /** Returns the value of CPSR (Current Program Status Register). |
73 | /** Returns the value of CPSR (Current Program Status Register). */ |
74 | */ |
- | |
75 | GEN_STATUS_READ(current, cpsr) |
74 | GEN_STATUS_READ(current, cpsr) |
76 | 75 | ||
77 | 76 | ||
78 | /** Sets control bits of CPSR |
77 | /** Sets control bits of CPSR. */ |
79 | */ |
- | |
80 | GEN_STATUS_WRITE(current, cpsr, control, c); |
78 | GEN_STATUS_WRITE(current, cpsr, control, c); |
81 | 79 | ||
82 | 80 | ||
83 | /** Returns the value of SPSR (Saved Program Status Register). |
81 | /** Returns the value of SPSR (Saved Program Status Register). */ |
84 | */ |
- | |
85 | GEN_STATUS_READ(saved, spsr) |
82 | GEN_STATUS_READ(saved, spsr) |
86 | 83 | ||
87 | 84 | ||
88 | - | ||
89 | #endif |
85 | #endif |
90 | 86 | ||
91 | /** @} |
87 | /** @} |
92 | */ |
88 | */ |