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4651 pillai 1
/*
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 * Copyright (c) 2009 Vineeth Pillai
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup genarch    
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 * @{
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 */
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/** @file
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 * @brief   Describes the pl050 keyboard/mouse controller
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 */
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/**
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 * This file implements pl050 specific functions for keyboard and mouse
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 */
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#ifndef KERN_genarch_PL050_H
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#define KERN_genarch_PL050_H
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#include <ddi/irq.h>
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#include <arch/types.h>
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#include <console/chardev.h>
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#include <typedefs.h>
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/*
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 * pl050 register offsets from the base address
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 */
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#define PL050_CR    0x00
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#define PL050_STAT  0x04
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#define PL050_DATA  0x08
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#define PL050_CLOCKDIV  0x0C
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#define PL050_INTRSTAT  0x10
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/*
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 * Control Register Bits
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 */
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#define PL050_CR_TYPE   (1 << 5)    /* Type 0: PS2/AT mode, 1: No Line control bit mode */
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#define PL050_CR_RXINTR (1 << 4)    /* Recieve Interrupt Enable */
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#define PL050_CR_TXINTR (1 << 3)    /* Transmit Interrupt Enable */
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#define PL050_CR_INTR   (1 << 2)    /* Interrupt Enable */
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#define PL050_CR_FKMID  (1 << 1)    /* Force KMI Data Low */
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#define PL050_CR_FKMIC  1       /* Force KMI Clock Low */
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/*
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 * Status register bits
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 */
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#define PL050_STAT_TXEMPTY  (1 << 6)    /* 1: Transmit register empty */
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#define PL050_STAT_TXBUSY   (1 << 5)    /* 1: Busy, sending data */
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#define PL050_STAT_RXFULL   (1 << 4)    /* 1: register Full */
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#define PL050_STAT_RXBUSY   (1 << 3)    /* 1: Busy, recieving Data */
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#define PL050_STAT_RXPARITY (1 << 2)    /* odd parity of the last bit recieved */
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#define PL050_STAT_KMIC     (1 << 1)    /* status of KMICLKIN */
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#define PL050_STAT_KMID     1       /* status of KMIDATAIN */
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/*
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 * Interrupt status register bits.
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 */
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#define PL050_TX_INTRSTAT   (1 << 1)    /* Transmit intr asserted */
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#define PL050_RX_INTRSTAT   1       /* Recieve intr asserted */
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typedef struct {
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    ioport8_t *base;
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    ioport8_t *data;
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    ioport8_t *status;
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    ioport8_t *ctrl;
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} pl050_t;
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typedef struct {
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    irq_t   irq;
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    pl050_t *pl050;
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    indev_t *kbrdin;
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} pl050_instance_t;
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extern pl050_instance_t *pl050_init(pl050_t *, inr_t);
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extern void pl050_wire(pl050_instance_t *, indev_t *);
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#endif
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/** @}
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 */