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| Rev | Author | Line No. | Line |
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| 1903 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2006 Jakub Jermar |
| 1903 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup sparc64 |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 35 | #include <smp/ipi.h> |
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| 1904 | jermar | 36 | #include <cpu.h> |
| 2089 | decky | 37 | #include <arch.h> |
| 1904 | jermar | 38 | #include <arch/cpu.h> |
| 39 | #include <arch/asm.h> |
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| 40 | #include <config.h> |
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| 41 | #include <mm/tlb.h> |
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| 2134 | jermar | 42 | #include <arch/mm/cache.h> |
| 1904 | jermar | 43 | #include <arch/interrupt.h> |
| 44 | #include <arch/trap/interrupt.h> |
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| 45 | #include <arch/barrier.h> |
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| 46 | #include <preemption.h> |
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| 47 | #include <time/delay.h> |
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| 48 | #include <panic.h> |
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| 1903 | jermar | 49 | |
| 1904 | jermar | 50 | /** Invoke function on another processor. |
| 51 | * |
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| 52 | * Currently, only functions without arguments are supported. |
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| 53 | * Supporting more arguments in the future should be no big deal. |
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| 54 | * |
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| 55 | * Interrupts must be disabled prior to this call. |
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| 56 | * |
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| 57 | * @param mid MID of the target processor. |
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| 58 | * @param func Function to be invoked. |
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| 59 | */ |
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| 60 | static void cross_call(int mid, void (* func)(void)) |
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| 61 | { |
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| 62 | uint64_t status; |
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| 63 | bool done; |
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| 64 | |||
| 65 | /* |
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| 2048 | jermar | 66 | * This function might enable interrupts for a while. |
| 1904 | jermar | 67 | * In order to prevent migration to another processor, |
| 68 | * we explicitly disable preemption. |
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| 69 | */ |
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| 70 | |||
| 71 | preemption_disable(); |
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| 72 | |||
| 73 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
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| 74 | if (status & INTR_DISPATCH_STATUS_BUSY) |
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| 75 | panic("Interrupt Dispatch Status busy bit set\n"); |
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| 76 | |||
| 77 | do { |
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| 2054 | jermar | 78 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) |
| 79 | func); |
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| 1904 | jermar | 80 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0); |
| 81 | asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0); |
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| 2134 | jermar | 82 | asi_u64_write(ASI_UDB_INTR_W, |
| 83 | (mid << INTR_VEC_DISPATCH_MID_SHIFT) | |
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| 84 | ASI_UDB_INTR_W_DISPATCH, 0); |
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| 1904 | jermar | 85 | |
| 86 | membar(); |
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| 87 | |||
| 88 | do { |
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| 89 | status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
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| 90 | } while (status & INTR_DISPATCH_STATUS_BUSY); |
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| 91 | |||
| 92 | done = !(status & INTR_DISPATCH_STATUS_NACK); |
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| 93 | if (!done) { |
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| 94 | /* |
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| 95 | * Prevent deadlock. |
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| 96 | */ |
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| 97 | (void) interrupts_enable(); |
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| 98 | delay(20 + (tick_read() & 0xff)); |
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| 99 | (void) interrupts_disable(); |
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| 100 | } |
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| 101 | } while (done); |
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| 102 | |||
| 103 | preemption_enable(); |
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| 104 | } |
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| 105 | |||
| 106 | /* |
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| 107 | * Deliver IPI to all processors except the current one. |
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| 108 | * |
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| 109 | * The sparc64 architecture does not support any group addressing |
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| 110 | * which is found, for instance, on ia32 and amd64. Therefore we |
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| 111 | * need to simulate the broadcast by sending the message to |
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| 112 | * all target processors step by step. |
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| 113 | * |
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| 114 | * We assume that interrupts are disabled. |
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| 115 | * |
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| 116 | * @param ipi IPI number. |
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| 117 | */ |
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| 1903 | jermar | 118 | void ipi_broadcast_arch(int ipi) |
| 119 | { |
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| 1904 | jermar | 120 | int i; |
| 121 | |||
| 122 | void (* func)(void); |
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| 123 | |||
| 124 | switch (ipi) { |
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| 125 | case IPI_TLB_SHOOTDOWN: |
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| 126 | func = tlb_shootdown_ipi_recv; |
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| 127 | break; |
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| 2134 | jermar | 128 | #if (defined(CONFIG_SMP) && (defined(CONFIG_VIRT_IDX_DCACHE))) |
| 129 | case IPI_DCACHE_SHOOTDOWN: |
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| 130 | func = dcache_shootdown_ipi_recv; |
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| 131 | break; |
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| 132 | #endif |
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| 1904 | jermar | 133 | default: |
| 134 | panic("Unknown IPI (%d).\n", ipi); |
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| 135 | break; |
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| 136 | } |
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| 137 | |||
| 138 | /* |
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| 139 | * As long as we don't support hot-plugging |
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| 140 | * or hot-unplugging of CPUs, we can walk |
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| 141 | * the cpus array and read processor's MID |
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| 142 | * without locking. |
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| 143 | */ |
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| 144 | |||
| 145 | for (i = 0; i < config.cpu_active; i++) { |
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| 146 | if (&cpus[i] == CPU) |
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| 147 | continue; /* skip the current CPU */ |
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| 148 | |||
| 149 | cross_call(cpus[i].arch.mid, func); |
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| 150 | } |
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| 1903 | jermar | 151 | } |
| 152 | |||
| 153 | /** @} |
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| 154 | */ |