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| Rev | Author | Line No. | Line |
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| 619 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
| 619 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1822 | jermar | 29 | /** @addtogroup sparc64mm |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1860 | jermar | 35 | #ifndef KERN_sparc64_MMU_H_ |
| 36 | #define KERN_sparc64_MMU_H_ |
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| 619 | jermar | 37 | |
| 1849 | jermar | 38 | /* LSU Control Register ASI. */ |
| 619 | jermar | 39 | #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
| 40 | |||
| 1849 | jermar | 41 | /* I-MMU ASIs. */ |
| 619 | jermar | 42 | #define ASI_IMMU 0x50 |
| 43 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
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| 44 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
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| 45 | #define ASI_ITLB_DATA_IN_REG 0x54 |
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| 46 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
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| 47 | #define ASI_ITLB_TAG_READ_REG 0x56 |
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| 48 | #define ASI_IMMU_DEMAP 0x57 |
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| 49 | |||
| 1849 | jermar | 50 | /* Virtual Addresses within ASI_IMMU. */ |
| 1891 | jermar | 51 | #define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ |
| 619 | jermar | 52 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
| 53 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
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| 54 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
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| 55 | |||
| 1849 | jermar | 56 | /* D-MMU ASIs. */ |
| 619 | jermar | 57 | #define ASI_DMMU 0x58 |
| 58 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
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| 59 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
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| 60 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
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| 61 | #define ASI_DTLB_DATA_IN_REG 0x5c |
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| 62 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
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| 63 | #define ASI_DTLB_TAG_READ_REG 0x5e |
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| 64 | #define ASI_DMMU_DEMAP 0x5f |
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| 65 | |||
| 1849 | jermar | 66 | /* Virtual Addresses within ASI_DMMU. */ |
| 1891 | jermar | 67 | #define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ |
| 619 | jermar | 68 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
| 69 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
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| 70 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
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| 71 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
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| 72 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
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| 73 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
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| 74 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
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| 75 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
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| 76 | |||
| 1822 | jermar | 77 | #ifndef __ASM__ |
| 619 | jermar | 78 | |
| 1822 | jermar | 79 | #include <arch/asm.h> |
| 80 | #include <arch/barrier.h> |
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| 81 | #include <arch/types.h> |
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| 82 | #include <typedefs.h> |
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| 83 | |||
| 619 | jermar | 84 | /** LSU Control Register. */ |
| 85 | union lsu_cr_reg { |
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| 1780 | jermar | 86 | uint64_t value; |
| 619 | jermar | 87 | struct { |
| 88 | unsigned : 23; |
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| 89 | unsigned pm : 8; |
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| 90 | unsigned vm : 8; |
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| 91 | unsigned pr : 1; |
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| 92 | unsigned pw : 1; |
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| 93 | unsigned vr : 1; |
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| 94 | unsigned vw : 1; |
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| 95 | unsigned : 1; |
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| 96 | unsigned fm : 16; |
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| 97 | unsigned dm : 1; /**< D-MMU enable. */ |
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| 98 | unsigned im : 1; /**< I-MMU enable. */ |
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| 99 | unsigned dc : 1; /**< D-Cache enable. */ |
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| 100 | unsigned ic : 1; /**< I-Cache enable. */ |
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| 101 | |||
| 102 | } __attribute__ ((packed)); |
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| 103 | }; |
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| 104 | typedef union lsu_cr_reg lsu_cr_reg_t; |
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| 105 | |||
| 1823 | jermar | 106 | #endif /* !def __ASM__ */ |
| 619 | jermar | 107 | |
| 108 | #endif |
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| 1702 | cejka | 109 | |
| 1822 | jermar | 110 | /** @} |
| 1702 | cejka | 111 | */ |