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| Rev | Author | Line No. | Line |
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| 418 | jermar | 1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1784 | jermar | 29 | /** @addtogroup sparc64 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1860 | jermar | 35 | #ifndef KERN_sparc64_BARRIER_H_ |
| 36 | #define KERN_sparc64_BARRIER_H_ |
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| 418 | jermar | 37 | |
| 38 | /* |
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| 39 | * TODO: Implement true SPARC V9 memory barriers for macros below. |
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| 40 | */ |
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| 41 | #define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory") |
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| 42 | #define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory") |
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| 43 | |||
| 1891 | jermar | 44 | #define memory_barrier() __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory") |
| 45 | #define read_barrier() __asm__ volatile ("membar #LoadLoad\n" ::: "memory") |
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| 46 | #define write_barrier() __asm__ volatile ("membar #StoreStore\n" ::: "memory") |
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| 418 | jermar | 47 | |
| 760 | jermar | 48 | /** Flush Instruction Memory instruction. */ |
| 613 | jermar | 49 | static inline void flush(void) |
| 50 | { |
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| 51 | /* |
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| 760 | jermar | 52 | * The FLUSH instruction takes address parameter. |
| 53 | * As such, it may trap if the address is not found in DTLB. |
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| 1854 | jermar | 54 | * |
| 55 | * The entire kernel text is mapped by a locked ITLB and |
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| 56 | * DTLB entries. Therefore, when this function is called, |
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| 57 | * the %o7 register will always be in the range mapped by |
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| 58 | * DTLB. |
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| 613 | jermar | 59 | */ |
| 883 | jermar | 60 | |
| 1854 | jermar | 61 | __asm__ volatile ("flush %o7\n"); |
| 613 | jermar | 62 | } |
| 569 | jermar | 63 | |
| 760 | jermar | 64 | /** Memory Barrier instruction. */ |
| 758 | jermar | 65 | static inline void membar(void) |
| 66 | { |
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| 67 | __asm__ volatile ("membar #Sync\n"); |
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| 68 | } |
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| 69 | |||
| 418 | jermar | 70 | #endif |
| 1702 | cejka | 71 | |
| 1784 | jermar | 72 | /** @} |
| 1702 | cejka | 73 | */ |