Rev 1888 | Rev 2082 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2001-2004 Jakub Jermar |
| 1 | jermar | 3 | * All rights reserved. |
| 4 | * |
||
| 5 | * Redistribution and use in source and binary forms, with or without |
||
| 6 | * modification, are permitted provided that the following conditions |
||
| 7 | * are met: |
||
| 8 | * |
||
| 9 | * - Redistributions of source code must retain the above copyright |
||
| 10 | * notice, this list of conditions and the following disclaimer. |
||
| 11 | * - Redistributions in binary form must reproduce the above copyright |
||
| 12 | * notice, this list of conditions and the following disclaimer in the |
||
| 13 | * documentation and/or other materials provided with the distribution. |
||
| 14 | * - The name of the author may not be used to endorse or promote products |
||
| 15 | * derived from this software without specific prior written permission. |
||
| 16 | * |
||
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 27 | */ |
||
| 28 | |||
| 1888 | jermar | 29 | /** @addtogroup ia32 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
||
| 32 | /** @file |
||
| 33 | */ |
||
| 34 | |||
| 1888 | jermar | 35 | #ifndef KERN_ia32_ATOMIC_H_ |
| 36 | #define KERN_ia32_ATOMIC_H_ |
||
| 1 | jermar | 37 | |
| 38 | #include <arch/types.h> |
||
| 1100 | palkovsky | 39 | #include <arch/barrier.h> |
| 40 | #include <preemption.h> |
||
| 1104 | jermar | 41 | #include <typedefs.h> |
| 1 | jermar | 42 | |
| 475 | jermar | 43 | static inline void atomic_inc(atomic_t *val) { |
| 458 | decky | 44 | #ifdef CONFIG_SMP |
| 625 | palkovsky | 45 | __asm__ volatile ("lock incl %0\n" : "=m" (val->count)); |
| 115 | jermar | 46 | #else |
| 625 | palkovsky | 47 | __asm__ volatile ("incl %0\n" : "=m" (val->count)); |
| 458 | decky | 48 | #endif /* CONFIG_SMP */ |
| 115 | jermar | 49 | } |
| 1 | jermar | 50 | |
| 475 | jermar | 51 | static inline void atomic_dec(atomic_t *val) { |
| 458 | decky | 52 | #ifdef CONFIG_SMP |
| 625 | palkovsky | 53 | __asm__ volatile ("lock decl %0\n" : "=m" (val->count)); |
| 115 | jermar | 54 | #else |
| 625 | palkovsky | 55 | __asm__ volatile ("decl %0\n" : "=m" (val->count)); |
| 458 | decky | 56 | #endif /* CONFIG_SMP */ |
| 115 | jermar | 57 | } |
| 58 | |||
| 1104 | jermar | 59 | static inline long atomic_postinc(atomic_t *val) |
| 477 | vana | 60 | { |
| 1691 | palkovsky | 61 | long r = 1; |
| 627 | jermar | 62 | |
| 477 | vana | 63 | __asm__ volatile ( |
| 1691 | palkovsky | 64 | "lock xaddl %1, %0\n" |
| 1697 | palkovsky | 65 | : "=m" (val->count), "+r" (r) |
| 477 | vana | 66 | ); |
| 627 | jermar | 67 | |
| 477 | vana | 68 | return r; |
| 69 | } |
||
| 70 | |||
| 1104 | jermar | 71 | static inline long atomic_postdec(atomic_t *val) |
| 477 | vana | 72 | { |
| 1691 | palkovsky | 73 | long r = -1; |
| 627 | jermar | 74 | |
| 477 | vana | 75 | __asm__ volatile ( |
| 1691 | palkovsky | 76 | "lock xaddl %1, %0\n" |
| 1697 | palkovsky | 77 | : "=m" (val->count), "+r"(r) |
| 477 | vana | 78 | ); |
| 627 | jermar | 79 | |
| 477 | vana | 80 | return r; |
| 81 | } |
||
| 82 | |||
| 1024 | jermar | 83 | #define atomic_preinc(val) (atomic_postinc(val)+1) |
| 84 | #define atomic_predec(val) (atomic_postdec(val)-1) |
||
| 477 | vana | 85 | |
| 1780 | jermar | 86 | static inline uint32_t test_and_set(atomic_t *val) { |
| 87 | uint32_t v; |
||
| 115 | jermar | 88 | |
| 89 | __asm__ volatile ( |
||
| 90 | "movl $1, %0\n" |
||
| 259 | palkovsky | 91 | "xchgl %0, %1\n" |
| 625 | palkovsky | 92 | : "=r" (v),"=m" (val->count) |
| 115 | jermar | 93 | ); |
| 94 | |||
| 95 | return v; |
||
| 96 | } |
||
| 97 | |||
| 1104 | jermar | 98 | /** ia32 specific fast spinlock */ |
| 1100 | palkovsky | 99 | static inline void atomic_lock_arch(atomic_t *val) |
| 100 | { |
||
| 1780 | jermar | 101 | uint32_t tmp; |
| 115 | jermar | 102 | |
| 1100 | palkovsky | 103 | preemption_disable(); |
| 104 | __asm__ volatile ( |
||
| 105 | "0:;" |
||
| 106 | #ifdef CONFIG_HT |
||
| 107 | "pause;" /* Pentium 4's HT love this instruction */ |
||
| 108 | #endif |
||
| 109 | "mov %0, %1;" |
||
| 110 | "testl %1, %1;" |
||
| 1104 | jermar | 111 | "jnz 0b;" /* Lightweight looping on locked spinlock */ |
| 1100 | palkovsky | 112 | |
| 113 | "incl %1;" /* now use the atomic operation */ |
||
| 114 | "xchgl %0, %1;" |
||
| 115 | "testl %1, %1;" |
||
| 116 | "jnz 0b;" |
||
| 117 | : "=m"(val->count),"=r"(tmp) |
||
| 118 | ); |
||
| 119 | /* |
||
| 120 | * Prevent critical section code from bleeding out this way up. |
||
| 121 | */ |
||
| 122 | CS_ENTER_BARRIER(); |
||
| 123 | } |
||
| 1 | jermar | 124 | |
| 125 | #endif |
||
| 1702 | cejka | 126 | |
| 1888 | jermar | 127 | /** @} |
| 1702 | cejka | 128 | */ |