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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4666 | pillai | 1 | # |
| 2 | # Copyright (c) 2009 Vineeth Pillai |
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| 3 | # All rights reserved. |
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| 4 | # |
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| 5 | # Redistribution and use in source and binary forms, with or without |
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| 6 | # modification, are permitted provided that the following conditions |
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| 7 | # are met: |
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| 8 | # |
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| 9 | # - Redistributions of source code must retain the above copyright |
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| 10 | # notice, this list of conditions and the following disclaimer. |
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| 11 | # - Redistributions in binary form must reproduce the above copyright |
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| 12 | # notice, this list of conditions and the following disclaimer in the |
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| 13 | # documentation and/or other materials provided with the distribution. |
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| 14 | # - The name of the author may not be used to endorse or promote products |
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| 15 | # derived from this software without specific prior written permission. |
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| 16 | # |
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | # |
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| 28 | |||
| 29 | .text |
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| 30 | |||
| 31 | .global irq_exception_entry |
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| 32 | .global fiq_exception_entry |
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| 33 | .global data_abort_exception_entry |
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| 34 | .global prefetch_abort_exception_entry |
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| 35 | .global undef_instr_exception_entry |
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| 36 | .global swi_exception_entry |
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| 37 | .global reset_exception_entry |
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| 38 | |||
| 39 | |||
| 40 | # Switches to kernel stack and saves all registers there. |
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| 41 | # |
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| 42 | # The stack frame created by the function looks like: |
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| 43 | # |
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| 44 | # |_________________| |
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| 45 | # | | |
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| 46 | # | SPSR | |
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| 47 | # | | |
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| 48 | # |_________________| |
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| 49 | # | Stack Pointer | |
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| 50 | # | of | |
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| 51 | # | Previous Mode | |
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| 52 | # |_________________| |
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| 53 | # | Return address | |
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| 54 | # | of | |
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| 55 | # | Previous Mode | |
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| 56 | # |_________________| |
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| 57 | # | R0 - R12 | |
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| 58 | # | of | |
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| 59 | # | Previous Mode | |
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| 60 | # |_________________| |
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| 61 | # | Return address | |
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| 62 | # | from | |
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| 63 | # |Exception Handler| |
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| 64 | # |_________________| |
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| 65 | # | | |
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| 66 | # |
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| 67 | # |
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| 68 | |||
| 69 | .macro SAVE_REGS_TO_STACK |
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| 70 | stmfd r13!, {r0-r3} |
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| 71 | mov r3, sp |
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| 72 | add sp, sp, #16 |
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| 73 | mrs r1, cpsr |
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| 74 | bic r1, r1, #0x1f |
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| 75 | mrs r2, spsr |
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| 76 | and r0, r2, #0x1f |
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| 77 | cmp r0, #0x10 |
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| 78 | bne 1f |
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| 79 | |||
| 80 | # prev mode was usermode |
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| 81 | mov r0, lr |
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| 82 | |||
| 83 | # Switch to supervisor mode |
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| 84 | orr r1, r1, #0x13 |
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| 85 | msr cpsr_c, r1 |
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| 86 | |||
| 87 | # Load sp with [supervisor_sp] |
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| 88 | ldr r13, =supervisor_sp |
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| 89 | ldr r13, [r13] |
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| 90 | |||
| 91 | # Populate the stack frame |
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| 92 | msr spsr, r2 |
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| 93 | mov lr, r0 |
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| 94 | stmfd r13!, {lr} |
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| 95 | stmfd r13!, {r4-r12} |
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| 96 | ldmfd r3!, {r4-r7} |
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| 97 | stmfd r13!, {r4-r7} |
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| 98 | stmfd r13!, {r13, lr}^ |
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| 99 | stmfd r13!, {r2} |
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| 100 | b 2f |
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| 101 | |||
| 102 | # mode was not usermode |
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| 103 | 1: |
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| 104 | # Switch to previous mode which is undoubtedly the supervisor mode |
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| 105 | orr r1, r1, r0 |
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| 106 | mov r0, lr |
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| 107 | msr cpsr_c, r1 |
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| 108 | |||
| 109 | # Populate the stack frame |
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| 110 | mov r1, sp |
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| 111 | stmfd r13!, {r0} |
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| 112 | stmfd r13!, {r4-r12} |
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| 113 | |||
| 114 | # Store r0-r3 in r4-r7 and then push it on to stack |
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| 115 | ldmfd r3!, {r4-r7} |
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| 116 | stmfd r13!, {r4-r7} |
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| 117 | |||
| 118 | # Push return address and stack pointer on to stack |
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| 119 | stmfd r13!, {lr} |
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| 120 | stmfd r13!, {r1} |
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| 121 | mov lr, r0 |
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| 122 | msr spsr, r2 |
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| 123 | stmfd r13!, {r2} |
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| 124 | 2: |
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| 125 | .endm |
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| 126 | |||
| 127 | .macro LOAD_REGS_FROM_STACK |
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| 128 | ldmfd r13!, {r0} |
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| 129 | msr spsr, r0 |
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| 130 | and r0, r0, #0x1f |
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| 131 | cmp r0, #0x10 |
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| 132 | bne 1f |
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| 133 | |||
| 134 | # return to user mode |
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| 135 | ldmfd r13!, {r13, lr}^ |
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| 136 | b 2f |
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| 137 | |||
| 138 | # return to non-user mode |
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| 139 | 1: |
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| 140 | ldmfd r13!, {r1, lr} |
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| 141 | |||
| 142 | 2: |
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| 143 | ldmfd r13!, {r0-r12, pc}^ |
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| 144 | .endm |
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| 145 | |||
| 146 | reset_exception_entry: |
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| 147 | SAVE_REGS_TO_STACK |
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| 148 | mov r0, #0 |
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| 149 | mov r1, r13 |
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| 150 | bl exc_dispatch |
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| 151 | LOAD_REGS_FROM_STACK |
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| 152 | |||
| 153 | irq_exception_entry: |
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| 154 | sub lr, lr, #4 |
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| 155 | SAVE_REGS_TO_STACK |
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| 156 | mov r0, #5 |
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| 157 | mov r1, r13 |
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| 158 | bl exc_dispatch |
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| 159 | LOAD_REGS_FROM_STACK |
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| 160 | |||
| 161 | fiq_exception_entry: |
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| 162 | sub lr, lr, #4 |
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| 163 | SAVE_REGS_TO_STACK |
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| 164 | mov r0, #6 |
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| 165 | mov r1, r13 |
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| 166 | bl exc_dispatch |
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| 167 | LOAD_REGS_FROM_STACK |
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| 168 | |||
| 169 | undef_instr_exception_entry: |
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| 170 | SAVE_REGS_TO_STACK |
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| 171 | mov r0, #1 |
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| 172 | mov r1, r13 |
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| 173 | bl exc_dispatch |
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| 174 | LOAD_REGS_FROM_STACK |
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| 175 | |||
| 176 | prefetch_abort_exception_entry: |
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| 177 | sub lr, lr, #4 |
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| 178 | SAVE_REGS_TO_STACK |
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| 179 | mov r0, #3 |
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| 180 | mov r1, r13 |
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| 181 | bl exc_dispatch |
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| 182 | LOAD_REGS_FROM_STACK |
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| 183 | |||
| 184 | data_abort_exception_entry: |
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| 185 | sub lr, lr, #8 |
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| 186 | SAVE_REGS_TO_STACK |
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| 187 | mov r0, #4 |
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| 188 | mov r1, r13 |
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| 189 | bl exc_dispatch |
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| 190 | LOAD_REGS_FROM_STACK |
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| 191 | |||
| 192 | swi_exception_entry: |
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| 193 | ldr r13, =exc_stack |
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| 194 | SAVE_REGS_TO_STACK |
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| 195 | mov r0, #2 |
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| 196 | mov r1, r13 |
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| 197 | bl exc_dispatch |
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| 198 | LOAD_REGS_FROM_STACK |
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| 199 |