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4651 pillai 1
/*
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 * Copyright (c) 2009 Vineeth Pillai
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup arm32integratorcp
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 *  @brief Integratorcp machine specific parts.
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 *  @ingroup arm32
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 * @{
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 */
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/** @file
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 *  @brief Integratorcp peripheries drivers declarations.
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 */
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#ifndef KERN_arm32_ICP_H_
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#define KERN_arm32_ICP_H_
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#include <arch/machine_func.h>
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/** Last interrupt number (beginning from 0) whose status is probed
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 * from interrupt controller
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 */
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#define ICP_IRQC_MAX_IRQ  8
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#define ICP_KBD_IRQ       3
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#define ICP_TIMER_IRQ    6
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/** Timer frequency */
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#define ICP_TIMER_FREQ  10000
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#define ICP_UART			0x16000000
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#define ICP_KBD				0x18000000
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#define ICP_KBD_STAT			0x04
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#define ICP_KBD_DATA			0x08
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#define ICP_KBD_INTR_STAT		0x10
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#define ICP_RTC				0x13000000
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#define ICP_RTC1_LOAD_OFFSET		0x100
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#define ICP_RTC1_READ_OFFSET		0x104
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#define ICP_RTC1_CTL_OFFSET		0x108
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#define ICP_RTC1_INTRCLR_OFFSET		0x10C
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#define ICP_RTC1_INTRSTAT_OFFSET	0x114
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#define ICP_RTC1_BGLOAD_OFFSET		0x118
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#define ICP_RTC_CTL_VALUE		0x00E2
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#define ICP_IRQC			0x14000000
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#define ICP_IRQC_MASK_OFFSET		0xC
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#define ICP_IRQC_UNMASK_OFFSET		0x8
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#define ICP_FB				0x00800000
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#define ICP_FB_FRAME			(ICP_FB >> 12)
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#define ICP_FB_NUM_FRAME		512
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#define ICP_VGA				0xC0000000
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#define ICP_CMCR			0x10000000
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#define ICP_SDRAM_MASK			0x1C
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#define ICP_SDRAMCR_OFFSET		0x20
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typedef struct {
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        uintptr_t uart;
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        uintptr_t kbd_ctrl;
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        uintptr_t kbd_stat;
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        uintptr_t kbd_data;
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        uintptr_t kbd_intstat;
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        uintptr_t rtc;
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        uintptr_t rtc1_load;
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        uintptr_t rtc1_read;
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        uintptr_t rtc1_ctl;
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        uintptr_t rtc1_intrclr;
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        uintptr_t rtc1_intrstat;
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        uintptr_t rtc1_bgload;
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        uintptr_t irqc;
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        uintptr_t irqc_mask;
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        uintptr_t irqc_unmask;
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        uintptr_t vga;
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        uintptr_t cmcr;
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        uintptr_t sdramcr;
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} icp_hw_map_t;
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extern void icp_init(void);
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extern void icp_fb_init(void);
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extern void icp_output_init(void);
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extern void icp_input_init(void);
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extern void icp_release_console(void);
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extern void icp_grab_console(void);
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extern void icp_timer_irq_start(void);
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extern void icp_cpu_halt(void);
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extern void icp_irq_exception(int exc_no, istate_t *istate);
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extern uintptr_t icp_get_memory_size(void);
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extern uintptr_t icp_get_fb_address(void);
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extern void icp_fb_init(void);
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extern void icp_frame_init(void);
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#endif
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/** @}
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 */