Subversion Repositories HelenOS-historic

Rev

Rev 532 | Rev 703 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
119 jermar 1 
Memory management
2 
=================
3 
 
4 
SPARTAN kernel deploys generic interface for 4-level page tables,
5 
no matter what the real underlying hardware architecture is.
6 
 
7 
 
8 
 VADDR
9 
 +-----------------------------------------------------------------------------+
10 
 |   PTL0_INDEX  |   PTL1_INDEX   |   PTL2_INDEX   |   PTL3_INDEX   |   OFFSET |
11 
 +-----------------------------------------------------------------------------+
12 
 
13 
 
14 
 PTL0                   PTL1                   PTL2                   PTL3
15 
 +--------+             +--------+             +--------+             +--------+
16 
 |        |             |        |             |  PTL3  | -----\      |        |
17 
 |        |             |        |             +--------+      |      |        |
18 
 |        |             +--------+             |        |      |      |        |
19 
 |        |             |  PTL2  | -----\      |        |      |      |        |
20 
 |        |             +--------+      |      |        |      |      |        |
21 
 |        |             |        |      |      |        |      |      +--------+
22 
 +--------+             |        |      |      |        |      |      | FRAME  |
23 
 |  PTL1  | -----\      |        |      |      |        |      |      +--------+
24 
 +--------+      |      |        |      |      |        |      |      |        |
25 
 |        |      |      |        |      |      |        |      |      |        |
26 
 |        |      |      |        |      |      |        |      |      |        |
27 
 +--------+      \----> +--------+      \----> +--------+      \----> +--------+
28 
     ^
29 
     |
30 
     |
31 
 +--------+
32 
 |  PTL0  |
33 
 +--------+
34 
 
35 
 
36 
PTL0		Page Table Level 0 (Page Directory)
37 
PTL1		Page Table Level 1
38 
PTL2		Page Table Level 2
39 
PTL3		Page Table Level 3
40 
 
41 
PTL0_INDEX	Index into PTL0
42 
PTL1_INDEX	Index into PTL1
43 
PTL2_INDEX	Index into PTL2
44 
PTL3_INDEX	Index into PTL3
45 
 
46 
VADDR		Virtual address for which mapping is looked up
47 
FRAME		Physical address of memory frame to which VADDR is mapped
48 
 
49 
 
50 
On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are
51 
left out. TLB-only architectures are to define custom format for software page
52 
tables.