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570 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch/mm/tlb.h>
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#include <mm/tlb.h>
619 jermar 31
#include <arch/mm/frame.h>
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#include <arch/mm/page.h>
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#include <arch/mm/mmu.h>
877 jermar 34
#include <mm/asid.h>
570 jermar 35
#include <print.h>
617 jermar 36
#include <arch/types.h>
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#include <typedefs.h>
619 jermar 38
#include <config.h>
630 jermar 39
#include <arch/trap/trap.h>
863 jermar 40
#include <panic.h>
873 jermar 41
#include <arch/asm.h>
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#include <symtab.h>
894 jermar 43
 
883 jermar 44
#include <arch/drivers/fb.h>
895 jermar 45
#include <arch/drivers/i8042.h>
570 jermar 46
 
873 jermar 47
char *context_encoding[] = {
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	"Primary",
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	"Secondary",
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	"Nucleus",
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	"Reserved"
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};
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619 jermar 54
/** Initialize ITLB and DTLB.
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 *
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 * The goal of this function is to disable MMU
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 * so that both TLBs can be purged and new
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 * kernel 4M locked entry can be installed.
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 * After TLB is initialized, MMU is enabled
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 * again.
627 jermar 61
 *
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 * Switching MMU off imposes the requirement for
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 * the kernel to run in identity mapped environment.
619 jermar 64
 */
570 jermar 65
void tlb_arch_init(void)
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{
619 jermar 67
	tlb_tag_access_reg_t tag;
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	tlb_data_t data;
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	frame_address_t fr;
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	page_address_t pg;
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	fr.address = config.base;
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	pg.address = config.base;
646 jermar 74
 
619 jermar 75
	immu_disable();
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	dmmu_disable();
898 jermar 77
 
78
	/*
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	 * Demap everything, especially OpenFirmware.
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	 */
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	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
619 jermar 83
 
84
	/*
846 jermar 85
	 * We do identity mapping of 4M-page at 4M.
619 jermar 86
	 */
877 jermar 87
	tag.value = ASID_KERNEL;
619 jermar 88
	tag.vpn = pg.vpn;
89
 
90
	itlb_tag_access_write(tag.value);
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	dtlb_tag_access_write(tag.value);
92
 
93
	data.value = 0;
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	data.v = true;
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	data.size = PAGESIZE_4M;
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	data.pfn = fr.pfn;
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	data.l = true;
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	data.cp = 1;
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	data.cv = 1;
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	data.p = true;
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	data.w = true;
102
	data.g = true;
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104
	itlb_data_in_write(data.value);
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	dtlb_data_in_write(data.value);
106
 
627 jermar 107
	/*
108
	 * Register window traps can occur before MMU is enabled again.
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	 * This ensures that any such traps will be handled from 
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	 * kernel identity mapped trap handler.
111
	 */
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	trap_switch_trap_table();
113
 
619 jermar 114
	tlb_invalidate_all();
115
 
116
	dmmu_enable();
117
	immu_enable();
897 jermar 118
}
873 jermar 119
 
897 jermar 120
/** Insert privileged mapping into DMMU TLB.
121
 *
122
 * @param page Virtual page address.
123
 * @param frame Physical frame address.
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 * @param pagesize Page size.
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 * @param locked True for permanent mappings, false otherwise.
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 * @param cacheable True if the mapping is cacheable, false otherwise.
127
 */
128
void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
129
{
130
	tlb_tag_access_reg_t tag;
131
	tlb_data_t data;
132
	page_address_t pg;
133
	frame_address_t fr;
873 jermar 134
 
897 jermar 135
	pg.address = page;
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	fr.address = frame;
873 jermar 137
 
894 jermar 138
	tag.value = ASID_KERNEL;
139
	tag.vpn = pg.vpn;
140
 
141
	dtlb_tag_access_write(tag.value);
142
 
143
	data.value = 0;
144
	data.v = true;
897 jermar 145
	data.size = pagesize;
894 jermar 146
	data.pfn = fr.pfn;
897 jermar 147
	data.l = locked;
148
	data.cp = cacheable;
149
	data.cv = cacheable;
894 jermar 150
	data.p = true;
151
	data.w = true;
152
	data.g = true;
153
 
154
	dtlb_data_in_write(data.value);
570 jermar 155
}
156
 
863 jermar 157
/** ITLB miss handler. */
158
void fast_instruction_access_mmu_miss(void)
159
{
160
	panic("%s\n", __FUNCTION__);
161
}
162
 
163
/** DTLB miss handler. */
164
void fast_data_access_mmu_miss(void)
165
{
877 jermar 166
	tlb_tag_access_reg_t tag;
167
	__address tpc;
873 jermar 168
	char *tpc_str;
883 jermar 169
 
877 jermar 170
	tag.value = dtlb_tag_access_read();
171
	if (tag.context != ASID_KERNEL || tag.vpn == 0) {
172
		tpc = tpc_read();
173
		tpc_str = get_symtab_entry(tpc);
873 jermar 174
 
877 jermar 175
		printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
176
		printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
177
		panic("%s\n", __FUNCTION__);
178
	}
179
 
180
	/*
181
	 * Identity map piece of faulting kernel address space.
182
	 */
897 jermar 183
	dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
863 jermar 184
}
185
 
186
/** DTLB protection fault handler. */
187
void fast_data_access_protection(void)
188
{
189
	panic("%s\n", __FUNCTION__);
190
}
191
 
570 jermar 192
/** Print contents of both TLBs. */
193
void tlb_print(void)
194
{
195
	int i;
196
	tlb_data_t d;
197
	tlb_tag_read_reg_t t;
198
 
199
	printf("I-TLB contents:\n");
200
	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
201
		d.value = itlb_data_access_read(i);
613 jermar 202
		t.value = itlb_tag_read_read(i);
570 jermar 203
 
617 jermar 204
		printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
205
			i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
570 jermar 206
	}
207
 
208
	printf("D-TLB contents:\n");
209
	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
210
		d.value = dtlb_data_access_read(i);
613 jermar 211
		t.value = dtlb_tag_read_read(i);
570 jermar 212
 
617 jermar 213
		printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
214
			i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
570 jermar 215
	}
216
 
217
}
617 jermar 218
 
219
/** Invalidate all unlocked ITLB and DTLB entries. */
220
void tlb_invalidate_all(void)
221
{
222
	int i;
223
	tlb_data_t d;
224
	tlb_tag_read_reg_t t;
225
 
226
	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
227
		d.value = itlb_data_access_read(i);
228
		if (!d.l) {
229
			t.value = itlb_tag_read_read(i);
230
			d.v = false;
231
			itlb_tag_access_write(t.value);
232
			itlb_data_access_write(i, d.value);
233
		}
234
	}
235
 
236
	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
237
		d.value = dtlb_data_access_read(i);
238
		if (!d.l) {
239
			t.value = dtlb_tag_read_read(i);
240
			d.v = false;
241
			dtlb_tag_access_write(t.value);
242
			dtlb_data_access_write(i, d.value);
243
		}
244
	}
245
 
246
}
247
 
248
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
249
 *
250
 * @param asid Address Space ID.
251
 */
252
void tlb_invalidate_asid(asid_t asid)
253
{
254
	/* TODO: write asid to some Context register and encode the register in second parameter below. */
255
	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
256
	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
257
}
258
 
727 jermar 259
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
617 jermar 260
 *
261
 * @param asid Address Space ID.
727 jermar 262
 * @param page First page which to sweep out from ITLB and DTLB.
263
 * @param cnt Number of ITLB and DTLB entries to invalidate.
617 jermar 264
 */
727 jermar 265
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
617 jermar 266
{
727 jermar 267
	int i;
268
 
269
	for (i = 0; i < cnt; i++) {
270
		/* TODO: write asid to some Context register and encode the register in second parameter below. */
271
		itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
272
		dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
273
	}
617 jermar 274
}