Rev 619 | Rev 758 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 619 | jermar | 1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
||
| 3 | * All rights reserved. |
||
| 4 | * |
||
| 5 | * Redistribution and use in source and binary forms, with or without |
||
| 6 | * modification, are permitted provided that the following conditions |
||
| 7 | * are met: |
||
| 8 | * |
||
| 9 | * - Redistributions of source code must retain the above copyright |
||
| 10 | * notice, this list of conditions and the following disclaimer. |
||
| 11 | * - Redistributions in binary form must reproduce the above copyright |
||
| 12 | * notice, this list of conditions and the following disclaimer in the |
||
| 13 | * documentation and/or other materials provided with the distribution. |
||
| 14 | * - The name of the author may not be used to endorse or promote products |
||
| 15 | * derived from this software without specific prior written permission. |
||
| 16 | * |
||
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 27 | */ |
||
| 28 | |||
| 29 | #ifndef __sparc64_MMU_H__ |
||
| 30 | #define __sparc64_MMU_H__ |
||
| 31 | |||
| 32 | #include <arch/asm.h> |
||
| 33 | #include <arch/barrier.h> |
||
| 34 | #include <arch/types.h> |
||
| 35 | #include <typedefs.h> |
||
| 36 | |||
| 37 | /** LSU Control Register ASI. */ |
||
| 38 | #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
||
| 39 | |||
| 40 | /** I-MMU ASIs. */ |
||
| 41 | #define ASI_IMMU 0x50 |
||
| 42 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
||
| 43 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
||
| 44 | #define ASI_ITLB_DATA_IN_REG 0x54 |
||
| 45 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
||
| 46 | #define ASI_ITLB_TAG_READ_REG 0x56 |
||
| 47 | #define ASI_IMMU_DEMAP 0x57 |
||
| 48 | |||
| 49 | /** Virtual Addresses within ASI_IMMU. */ |
||
| 50 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
||
| 51 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
||
| 52 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
||
| 53 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
||
| 54 | |||
| 55 | /** D-MMU ASIs. */ |
||
| 56 | #define ASI_DMMU 0x58 |
||
| 57 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
||
| 58 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
||
| 59 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
||
| 60 | #define ASI_DTLB_DATA_IN_REG 0x5c |
||
| 61 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
||
| 62 | #define ASI_DTLB_TAG_READ_REG 0x5e |
||
| 63 | #define ASI_DMMU_DEMAP 0x5f |
||
| 64 | |||
| 65 | /** Virtual Addresses within ASI_DMMU. */ |
||
| 66 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
||
| 67 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
||
| 68 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
||
| 69 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
||
| 70 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
||
| 71 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
||
| 72 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
||
| 73 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
||
| 74 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
||
| 75 | |||
| 76 | |||
| 77 | /** LSU Control Register. */ |
||
| 78 | union lsu_cr_reg { |
||
| 79 | __u64 value; |
||
| 80 | struct { |
||
| 81 | unsigned : 23; |
||
| 82 | unsigned pm : 8; |
||
| 83 | unsigned vm : 8; |
||
| 84 | unsigned pr : 1; |
||
| 85 | unsigned pw : 1; |
||
| 86 | unsigned vr : 1; |
||
| 87 | unsigned vw : 1; |
||
| 88 | unsigned : 1; |
||
| 89 | unsigned fm : 16; |
||
| 90 | unsigned dm : 1; /**< D-MMU enable. */ |
||
| 91 | unsigned im : 1; /**< I-MMU enable. */ |
||
| 92 | unsigned dc : 1; /**< D-Cache enable. */ |
||
| 93 | unsigned ic : 1; /**< I-Cache enable. */ |
||
| 94 | |||
| 95 | } __attribute__ ((packed)); |
||
| 96 | }; |
||
| 97 | typedef union lsu_cr_reg lsu_cr_reg_t; |
||
| 98 | |||
| 99 | |||
| 100 | #define immu_enable() immu_set(true) |
||
| 101 | #define immu_disable() immu_set(false) |
||
| 102 | #define dmmu_enable() dmmu_set(true) |
||
| 103 | #define dmmu_disable() dmmu_set(false) |
||
| 104 | |||
| 105 | /** Disable or Enable IMMU. */ |
||
| 658 | jermar | 106 | static inline void immu_set(bool enable) |
| 619 | jermar | 107 | { |
| 108 | lsu_cr_reg_t cr; |
||
| 109 | |||
| 110 | cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
||
| 111 | cr.im = enable; |
||
| 112 | asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value); |
||
| 113 | flush(); |
||
| 114 | } |
||
| 115 | |||
| 116 | /** Disable or Enable DMMU. */ |
||
| 658 | jermar | 117 | static inline void dmmu_set(bool enable) |
| 619 | jermar | 118 | { |
| 119 | lsu_cr_reg_t cr; |
||
| 120 | |||
| 121 | cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
||
| 122 | cr.dm = enable; |
||
| 123 | asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value); |
||
| 124 | flush(); |
||
| 125 | } |
||
| 126 | |||
| 127 | #endif |