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418 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __sparc64_BARRIER_H__
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#define __sparc64_BARRIER_H__
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/*
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 * TODO: Implement true SPARC V9 memory barriers for macros below.
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 */
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#define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
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#define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
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#define memory_barrier()
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#define read_barrier()
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#define write_barrier()
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/** Flush Instruction Memory instruction. */
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static inline void flush(void)
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{
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    /*
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     * The FLUSH instruction takes address parameter.
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     * As such, it may trap if the address is not found in DTLB.
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     * However, JPS1 implementations are free to ignore the trap.
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     */
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    /*
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     * %i7 should provide address that is always mapped in DTLB
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     * as it is a pointer to kernel code.
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     */
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        __asm__ volatile ("flush %i7\n");
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}
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/** Memory Barrier instruction. */
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static inline void membar(void)
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{
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    __asm__ volatile ("membar #Sync\n");
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}
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#endif