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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | jermar | 1 | /* |
| 319 | jermar | 2 | * Copyright (C) 2003-2004 Jakub Jermar |
| 1 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #include <arch/mm/tlb.h> |
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| 727 | jermar | 30 | #include <mm/asid.h> |
| 730 | jermar | 31 | #include <genarch/mm/asid_fifo.h> |
| 1 | jermar | 32 | #include <mm/tlb.h> |
| 391 | jermar | 33 | #include <mm/page.h> |
| 703 | jermar | 34 | #include <mm/as.h> |
| 1 | jermar | 35 | #include <arch/cp0.h> |
| 36 | #include <panic.h> |
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| 37 | #include <arch.h> |
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| 268 | palkovsky | 38 | #include <symtab.h> |
| 391 | jermar | 39 | #include <synch/spinlock.h> |
| 40 | #include <print.h> |
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| 396 | jermar | 41 | #include <debug.h> |
| 268 | palkovsky | 42 | |
| 391 | jermar | 43 | static void tlb_refill_fail(struct exception_regdump *pstate); |
| 44 | static void tlb_invalid_fail(struct exception_regdump *pstate); |
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| 45 | static void tlb_modified_fail(struct exception_regdump *pstate); |
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| 46 | |||
| 394 | jermar | 47 | static pte_t *find_mapping_and_check(__address badvaddr); |
| 399 | jermar | 48 | |
| 396 | jermar | 49 | static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn); |
| 399 | jermar | 50 | static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); |
| 394 | jermar | 51 | |
| 391 | jermar | 52 | /** Initialize TLB |
| 53 | * |
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| 54 | * Initialize TLB. |
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| 55 | * Invalidate all entries and mark wired entries. |
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| 56 | */ |
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| 569 | jermar | 57 | void tlb_arch_init(void) |
| 389 | jermar | 58 | { |
| 599 | jermar | 59 | int i; |
| 60 | |||
| 730 | jermar | 61 | asid_fifo_init(); |
| 62 | |||
| 389 | jermar | 63 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
| 599 | jermar | 64 | cp0_entry_hi_write(0); |
| 65 | cp0_entry_lo0_write(0); |
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| 66 | cp0_entry_lo1_write(0); |
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| 389 | jermar | 67 | |
| 599 | jermar | 68 | /* Clear and initialize TLB. */ |
| 69 | |||
| 70 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
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| 71 | cp0_index_write(i); |
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| 72 | tlbwi(); |
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| 73 | } |
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| 612 | jermar | 74 | |
| 598 | jermar | 75 | |
| 389 | jermar | 76 | /* |
| 77 | * The kernel is going to make use of some wired |
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| 391 | jermar | 78 | * entries (e.g. mapping kernel stacks in kseg3). |
| 389 | jermar | 79 | */ |
| 80 | cp0_wired_write(TLB_WIRED); |
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| 81 | } |
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| 82 | |||
| 391 | jermar | 83 | /** Process TLB Refill Exception |
| 84 | * |
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| 85 | * Process TLB Refill Exception. |
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| 86 | * |
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| 87 | * @param pstate Interrupted register context. |
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| 88 | */ |
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| 317 | palkovsky | 89 | void tlb_refill(struct exception_regdump *pstate) |
| 1 | jermar | 90 | { |
| 396 | jermar | 91 | entry_lo_t lo; |
| 399 | jermar | 92 | entry_hi_t hi; |
| 391 | jermar | 93 | __address badvaddr; |
| 94 | pte_t *pte; |
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| 397 | jermar | 95 | |
| 391 | jermar | 96 | badvaddr = cp0_badvaddr_read(); |
| 397 | jermar | 97 | |
| 703 | jermar | 98 | spinlock_lock(&AS->lock); |
| 399 | jermar | 99 | |
| 394 | jermar | 100 | pte = find_mapping_and_check(badvaddr); |
| 101 | if (!pte) |
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| 391 | jermar | 102 | goto fail; |
| 103 | |||
| 104 | /* |
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| 394 | jermar | 105 | * Record access to PTE. |
| 391 | jermar | 106 | */ |
| 394 | jermar | 107 | pte->a = 1; |
| 391 | jermar | 108 | |
| 703 | jermar | 109 | prepare_entry_hi(&hi, AS->asid, badvaddr); |
| 403 | jermar | 110 | prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn); |
| 394 | jermar | 111 | |
| 391 | jermar | 112 | /* |
| 113 | * New entry is to be inserted into TLB |
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| 114 | */ |
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| 399 | jermar | 115 | cp0_entry_hi_write(hi.value); |
| 391 | jermar | 116 | if ((badvaddr/PAGE_SIZE) % 2 == 0) { |
| 396 | jermar | 117 | cp0_entry_lo0_write(lo.value); |
| 391 | jermar | 118 | cp0_entry_lo1_write(0); |
| 119 | } |
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| 120 | else { |
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| 121 | cp0_entry_lo0_write(0); |
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| 396 | jermar | 122 | cp0_entry_lo1_write(lo.value); |
| 391 | jermar | 123 | } |
| 612 | jermar | 124 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
| 391 | jermar | 125 | tlbwr(); |
| 126 | |||
| 703 | jermar | 127 | spinlock_unlock(&AS->lock); |
| 391 | jermar | 128 | return; |
| 129 | |||
| 130 | fail: |
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| 703 | jermar | 131 | spinlock_unlock(&AS->lock); |
| 391 | jermar | 132 | tlb_refill_fail(pstate); |
| 133 | } |
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| 134 | |||
| 394 | jermar | 135 | /** Process TLB Invalid Exception |
| 136 | * |
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| 137 | * Process TLB Invalid Exception. |
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| 138 | * |
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| 139 | * @param pstate Interrupted register context. |
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| 140 | */ |
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| 391 | jermar | 141 | void tlb_invalid(struct exception_regdump *pstate) |
| 142 | { |
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| 396 | jermar | 143 | tlb_index_t index; |
| 394 | jermar | 144 | __address badvaddr; |
| 396 | jermar | 145 | entry_lo_t lo; |
| 399 | jermar | 146 | entry_hi_t hi; |
| 394 | jermar | 147 | pte_t *pte; |
| 148 | |||
| 149 | badvaddr = cp0_badvaddr_read(); |
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| 150 | |||
| 151 | /* |
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| 152 | * Locate the faulting entry in TLB. |
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| 153 | */ |
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| 399 | jermar | 154 | hi.value = cp0_entry_hi_read(); |
| 155 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
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| 156 | cp0_entry_hi_write(hi.value); |
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| 394 | jermar | 157 | tlbp(); |
| 396 | jermar | 158 | index.value = cp0_index_read(); |
| 394 | jermar | 159 | |
| 703 | jermar | 160 | spinlock_lock(&AS->lock); |
| 394 | jermar | 161 | |
| 162 | /* |
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| 163 | * Fail if the entry is not in TLB. |
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| 164 | */ |
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| 396 | jermar | 165 | if (index.p) { |
| 166 | printf("TLB entry not found.\n"); |
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| 394 | jermar | 167 | goto fail; |
| 396 | jermar | 168 | } |
| 394 | jermar | 169 | |
| 170 | pte = find_mapping_and_check(badvaddr); |
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| 171 | if (!pte) |
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| 172 | goto fail; |
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| 173 | |||
| 174 | /* |
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| 175 | * Read the faulting TLB entry. |
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| 176 | */ |
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| 177 | tlbr(); |
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| 178 | |||
| 179 | /* |
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| 180 | * Record access to PTE. |
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| 181 | */ |
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| 182 | pte->a = 1; |
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| 183 | |||
| 403 | jermar | 184 | prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn); |
| 394 | jermar | 185 | |
| 186 | /* |
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| 187 | * The entry is to be updated in TLB. |
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| 188 | */ |
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| 189 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
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| 396 | jermar | 190 | cp0_entry_lo0_write(lo.value); |
| 394 | jermar | 191 | else |
| 396 | jermar | 192 | cp0_entry_lo1_write(lo.value); |
| 612 | jermar | 193 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
| 394 | jermar | 194 | tlbwi(); |
| 195 | |||
| 703 | jermar | 196 | spinlock_unlock(&AS->lock); |
| 394 | jermar | 197 | return; |
| 198 | |||
| 199 | fail: |
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| 703 | jermar | 200 | spinlock_unlock(&AS->lock); |
| 391 | jermar | 201 | tlb_invalid_fail(pstate); |
| 202 | } |
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| 203 | |||
| 394 | jermar | 204 | /** Process TLB Modified Exception |
| 205 | * |
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| 206 | * Process TLB Modified Exception. |
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| 207 | * |
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| 208 | * @param pstate Interrupted register context. |
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| 209 | */ |
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| 391 | jermar | 210 | void tlb_modified(struct exception_regdump *pstate) |
| 211 | { |
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| 396 | jermar | 212 | tlb_index_t index; |
| 394 | jermar | 213 | __address badvaddr; |
| 396 | jermar | 214 | entry_lo_t lo; |
| 399 | jermar | 215 | entry_hi_t hi; |
| 394 | jermar | 216 | pte_t *pte; |
| 217 | |||
| 218 | badvaddr = cp0_badvaddr_read(); |
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| 219 | |||
| 220 | /* |
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| 221 | * Locate the faulting entry in TLB. |
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| 222 | */ |
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| 399 | jermar | 223 | hi.value = cp0_entry_hi_read(); |
| 224 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
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| 225 | cp0_entry_hi_write(hi.value); |
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| 394 | jermar | 226 | tlbp(); |
| 396 | jermar | 227 | index.value = cp0_index_read(); |
| 394 | jermar | 228 | |
| 703 | jermar | 229 | spinlock_lock(&AS->lock); |
| 394 | jermar | 230 | |
| 231 | /* |
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| 232 | * Fail if the entry is not in TLB. |
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| 233 | */ |
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| 396 | jermar | 234 | if (index.p) { |
| 235 | printf("TLB entry not found.\n"); |
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| 394 | jermar | 236 | goto fail; |
| 396 | jermar | 237 | } |
| 394 | jermar | 238 | |
| 239 | pte = find_mapping_and_check(badvaddr); |
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| 240 | if (!pte) |
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| 241 | goto fail; |
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| 242 | |||
| 243 | /* |
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| 244 | * Fail if the page is not writable. |
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| 245 | */ |
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| 246 | if (!pte->w) |
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| 247 | goto fail; |
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| 248 | |||
| 249 | /* |
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| 250 | * Read the faulting TLB entry. |
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| 251 | */ |
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| 252 | tlbr(); |
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| 253 | |||
| 254 | /* |
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| 255 | * Record access and write to PTE. |
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| 256 | */ |
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| 257 | pte->a = 1; |
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| 403 | jermar | 258 | pte->lo.d = 1; |
| 394 | jermar | 259 | |
| 403 | jermar | 260 | prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn); |
| 394 | jermar | 261 | |
| 262 | /* |
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| 263 | * The entry is to be updated in TLB. |
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| 264 | */ |
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| 265 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
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| 396 | jermar | 266 | cp0_entry_lo0_write(lo.value); |
| 394 | jermar | 267 | else |
| 396 | jermar | 268 | cp0_entry_lo1_write(lo.value); |
| 612 | jermar | 269 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
| 394 | jermar | 270 | tlbwi(); |
| 271 | |||
| 703 | jermar | 272 | spinlock_unlock(&AS->lock); |
| 394 | jermar | 273 | return; |
| 274 | |||
| 275 | fail: |
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| 703 | jermar | 276 | spinlock_unlock(&AS->lock); |
| 391 | jermar | 277 | tlb_modified_fail(pstate); |
| 278 | } |
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| 279 | |||
| 280 | void tlb_refill_fail(struct exception_regdump *pstate) |
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| 281 | { |
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| 324 | palkovsky | 282 | char *symbol = ""; |
| 283 | char *sym2 = ""; |
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| 284 | |||
| 332 | palkovsky | 285 | char *s = get_symtab_entry(pstate->epc); |
| 286 | if (s) |
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| 287 | symbol = s; |
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| 288 | s = get_symtab_entry(pstate->ra); |
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| 289 | if (s) |
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| 290 | sym2 = s; |
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| 391 | jermar | 291 | panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2); |
| 1 | jermar | 292 | } |
| 293 | |||
| 391 | jermar | 294 | |
| 295 | void tlb_invalid_fail(struct exception_regdump *pstate) |
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| 1 | jermar | 296 | { |
| 268 | palkovsky | 297 | char *symbol = ""; |
| 298 | |||
| 332 | palkovsky | 299 | char *s = get_symtab_entry(pstate->epc); |
| 300 | if (s) |
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| 301 | symbol = s; |
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| 394 | jermar | 302 | panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol); |
| 1 | jermar | 303 | } |
| 304 | |||
| 391 | jermar | 305 | void tlb_modified_fail(struct exception_regdump *pstate) |
| 389 | jermar | 306 | { |
| 307 | char *symbol = ""; |
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| 308 | |||
| 309 | char *s = get_symtab_entry(pstate->epc); |
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| 310 | if (s) |
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| 311 | symbol = s; |
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| 394 | jermar | 312 | panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol); |
| 389 | jermar | 313 | } |
| 314 | |||
| 394 | jermar | 315 | /** Try to find PTE for faulting address |
| 316 | * |
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| 317 | * Try to find PTE for faulting address. |
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| 703 | jermar | 318 | * The AS->lock must be held on entry to this function. |
| 394 | jermar | 319 | * |
| 320 | * @param badvaddr Faulting virtual address. |
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| 321 | * |
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| 322 | * @return PTE on success, NULL otherwise. |
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| 323 | */ |
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| 324 | pte_t *find_mapping_and_check(__address badvaddr) |
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| 325 | { |
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| 396 | jermar | 326 | entry_hi_t hi; |
| 394 | jermar | 327 | pte_t *pte; |
| 328 | |||
| 396 | jermar | 329 | hi.value = cp0_entry_hi_read(); |
| 394 | jermar | 330 | |
| 331 | /* |
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| 332 | * Handler cannot succeed if the ASIDs don't match. |
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| 333 | */ |
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| 703 | jermar | 334 | if (hi.asid != AS->asid) { |
| 335 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
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| 394 | jermar | 336 | return NULL; |
| 396 | jermar | 337 | } |
| 703 | jermar | 338 | |
| 394 | jermar | 339 | /* |
| 703 | jermar | 340 | * Check if the mapping exists in page tables. |
| 341 | */ |
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| 756 | jermar | 342 | pte = page_mapping_find(AS, badvaddr); |
| 703 | jermar | 343 | if (pte && pte->lo.v) { |
| 344 | /* |
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| 345 | * Mapping found in page tables. |
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| 346 | * Immediately succeed. |
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| 347 | */ |
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| 348 | return pte; |
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| 349 | } else { |
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| 350 | /* |
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| 351 | * Mapping not found in page tables. |
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| 352 | * Resort to higher-level page fault handler. |
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| 353 | */ |
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| 354 | if (as_page_fault(badvaddr)) { |
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| 355 | /* |
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| 356 | * The higher-level page fault handler succeeded, |
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| 357 | * The mapping ought to be in place. |
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| 358 | */ |
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| 756 | jermar | 359 | pte = page_mapping_find(AS, badvaddr); |
| 703 | jermar | 360 | ASSERT(pte && pte->lo.v); |
| 361 | return pte; |
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| 362 | } |
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| 363 | } |
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| 364 | |||
| 365 | /* |
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| 394 | jermar | 366 | * Handler cannot succeed if badvaddr has no mapping. |
| 367 | */ |
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| 396 | jermar | 368 | if (!pte) { |
| 764 | palkovsky | 369 | printf("No such mapping: %P.\n", badvaddr); |
| 394 | jermar | 370 | return NULL; |
| 396 | jermar | 371 | } |
| 394 | jermar | 372 | |
| 373 | /* |
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| 374 | * Handler cannot succeed if the mapping is marked as invalid. |
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| 375 | */ |
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| 403 | jermar | 376 | if (!pte->lo.v) { |
| 396 | jermar | 377 | printf("Invalid mapping.\n"); |
| 394 | jermar | 378 | return NULL; |
| 396 | jermar | 379 | } |
| 394 | jermar | 380 | |
| 381 | return pte; |
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| 382 | } |
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| 383 | |||
| 396 | jermar | 384 | void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn) |
| 394 | jermar | 385 | { |
| 399 | jermar | 386 | lo->value = 0; |
| 394 | jermar | 387 | lo->g = g; |
| 388 | lo->v = v; |
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| 389 | lo->d = d; |
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| 390 | lo->c = c; |
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| 391 | lo->pfn = pfn; |
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| 392 | } |
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| 399 | jermar | 393 | |
| 394 | void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr) |
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| 395 | { |
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| 396 | hi->value = (((addr/PAGE_SIZE)/2)*PAGE_SIZE*2); |
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| 397 | hi->asid = asid; |
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| 398 | } |
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| 569 | jermar | 399 | |
| 594 | jermar | 400 | /** Print contents of TLB. */ |
| 569 | jermar | 401 | void tlb_print(void) |
| 402 | { |
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| 612 | jermar | 403 | page_mask_t mask; |
| 594 | jermar | 404 | entry_lo_t lo0, lo1; |
| 704 | jermar | 405 | entry_hi_t hi, hi_save; |
| 594 | jermar | 406 | int i; |
| 407 | |||
| 704 | jermar | 408 | hi_save.value = cp0_entry_hi_read(); |
| 409 | |||
| 594 | jermar | 410 | printf("TLB:\n"); |
| 411 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
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| 412 | cp0_index_write(i); |
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| 413 | tlbr(); |
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| 414 | |||
| 612 | jermar | 415 | mask.value = cp0_pagemask_read(); |
| 594 | jermar | 416 | hi.value = cp0_entry_hi_read(); |
| 417 | lo0.value = cp0_entry_lo0_read(); |
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| 418 | lo1.value = cp0_entry_lo1_read(); |
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| 419 | |||
| 612 | jermar | 420 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%B, pfn[0]=%d\n" |
| 421 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%B, pfn[1]=%d\n", |
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| 422 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
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| 594 | jermar | 423 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
| 424 | } |
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| 704 | jermar | 425 | |
| 426 | cp0_entry_hi_write(hi_save.value); |
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| 569 | jermar | 427 | } |
| 598 | jermar | 428 | |
| 618 | jermar | 429 | /** Invalidate all not wired TLB entries. */ |
| 598 | jermar | 430 | void tlb_invalidate_all(void) |
| 431 | { |
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| 599 | jermar | 432 | ipl_t ipl; |
| 433 | entry_lo_t lo0, lo1; |
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| 704 | jermar | 434 | entry_hi_t hi_save; |
| 598 | jermar | 435 | int i; |
| 436 | |||
| 704 | jermar | 437 | hi_save.value = cp0_entry_hi_read(); |
| 599 | jermar | 438 | ipl = interrupts_disable(); |
| 598 | jermar | 439 | |
| 618 | jermar | 440 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
| 598 | jermar | 441 | cp0_index_write(i); |
| 599 | jermar | 442 | tlbr(); |
| 443 | |||
| 444 | lo0.value = cp0_entry_lo0_read(); |
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| 445 | lo1.value = cp0_entry_lo1_read(); |
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| 446 | |||
| 447 | lo0.v = 0; |
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| 448 | lo1.v = 0; |
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| 449 | |||
| 450 | cp0_entry_lo0_write(lo0.value); |
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| 451 | cp0_entry_lo1_write(lo1.value); |
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| 452 | |||
| 598 | jermar | 453 | tlbwi(); |
| 454 | } |
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| 599 | jermar | 455 | |
| 456 | interrupts_restore(ipl); |
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| 704 | jermar | 457 | cp0_entry_hi_write(hi_save.value); |
| 598 | jermar | 458 | } |
| 459 | |||
| 460 | /** Invalidate all TLB entries belonging to specified address space. |
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| 461 | * |
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| 462 | * @param asid Address space identifier. |
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| 463 | */ |
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| 464 | void tlb_invalidate_asid(asid_t asid) |
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| 465 | { |
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| 599 | jermar | 466 | ipl_t ipl; |
| 467 | entry_lo_t lo0, lo1; |
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| 704 | jermar | 468 | entry_hi_t hi, hi_save; |
| 598 | jermar | 469 | int i; |
| 470 | |||
| 599 | jermar | 471 | ASSERT(asid != ASID_INVALID); |
| 472 | |||
| 704 | jermar | 473 | hi_save.value = cp0_entry_hi_read(); |
| 599 | jermar | 474 | ipl = interrupts_disable(); |
| 475 | |||
| 598 | jermar | 476 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
| 477 | cp0_index_write(i); |
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| 478 | tlbr(); |
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| 479 | |||
| 599 | jermar | 480 | hi.value = cp0_entry_hi_read(); |
| 481 | |||
| 598 | jermar | 482 | if (hi.asid == asid) { |
| 599 | jermar | 483 | lo0.value = cp0_entry_lo0_read(); |
| 484 | lo1.value = cp0_entry_lo1_read(); |
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| 485 | |||
| 486 | lo0.v = 0; |
||
| 487 | lo1.v = 0; |
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| 488 | |||
| 489 | cp0_entry_lo0_write(lo0.value); |
||
| 490 | cp0_entry_lo1_write(lo1.value); |
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| 491 | |||
| 598 | jermar | 492 | tlbwi(); |
| 493 | } |
||
| 494 | } |
||
| 599 | jermar | 495 | |
| 496 | interrupts_restore(ipl); |
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| 704 | jermar | 497 | cp0_entry_hi_write(hi_save.value); |
| 598 | jermar | 498 | } |
| 499 | |||
| 727 | jermar | 500 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
| 598 | jermar | 501 | * |
| 502 | * @param asid Address space identifier. |
||
| 727 | jermar | 503 | * @param page First page whose TLB entry is to be invalidated. |
| 504 | * @param cnt Number of entries to invalidate. |
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| 598 | jermar | 505 | */ |
| 727 | jermar | 506 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
| 598 | jermar | 507 | { |
| 727 | jermar | 508 | int i; |
| 599 | jermar | 509 | ipl_t ipl; |
| 510 | entry_lo_t lo0, lo1; |
||
| 704 | jermar | 511 | entry_hi_t hi, hi_save; |
| 598 | jermar | 512 | tlb_index_t index; |
| 513 | |||
| 599 | jermar | 514 | ASSERT(asid != ASID_INVALID); |
| 515 | |||
| 704 | jermar | 516 | hi_save.value = cp0_entry_hi_read(); |
| 599 | jermar | 517 | ipl = interrupts_disable(); |
| 518 | |||
| 727 | jermar | 519 | for (i = 0; i < cnt; i++) { |
| 520 | hi.value = 0; |
||
| 521 | prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
||
| 522 | cp0_entry_hi_write(hi.value); |
||
| 599 | jermar | 523 | |
| 727 | jermar | 524 | tlbp(); |
| 525 | index.value = cp0_index_read(); |
||
| 598 | jermar | 526 | |
| 727 | jermar | 527 | if (!index.p) { |
| 528 | /* Entry was found, index register contains valid index. */ |
||
| 529 | tlbr(); |
||
| 599 | jermar | 530 | |
| 727 | jermar | 531 | lo0.value = cp0_entry_lo0_read(); |
| 532 | lo1.value = cp0_entry_lo1_read(); |
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| 599 | jermar | 533 | |
| 727 | jermar | 534 | lo0.v = 0; |
| 535 | lo1.v = 0; |
||
| 599 | jermar | 536 | |
| 727 | jermar | 537 | cp0_entry_lo0_write(lo0.value); |
| 538 | cp0_entry_lo1_write(lo1.value); |
||
| 599 | jermar | 539 | |
| 727 | jermar | 540 | tlbwi(); |
| 541 | } |
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| 598 | jermar | 542 | } |
| 599 | jermar | 543 | |
| 544 | interrupts_restore(ipl); |
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| 704 | jermar | 545 | cp0_entry_hi_write(hi_save.value); |
| 598 | jermar | 546 | } |