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1 jermar 1
/*
2
 * Copyright (C) 2001-2004 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
#include <arch/types.h>
11 jermar 30
#include <arch/smp/apic.h>
31
#include <arch/smp/ap.h>
34 jermar 32
#include <arch/smp/mps.h>
1 jermar 33
#include <mm/page.h>
34
#include <time/delay.h>
576 palkovsky 35
#include <interrupt.h>
1 jermar 36
#include <arch/interrupt.h>
37
#include <print.h>
38
#include <arch/asm.h>
39
#include <arch.h>
40
 
458 decky 41
#ifdef CONFIG_SMP
16 jermar 42
 
1 jermar 43
/*
512 jermar 44
 * Advanced Programmable Interrupt Controller for SMP systems.
1 jermar 45
 * Tested on:
112 jermar 46
 *	Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
523 jermar 47
 *	Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
516 jermar 48
 *	VMware Workstation 5.5 with 2 CPUs
1 jermar 49
 *	ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
437 decky 50
 *	ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
51
 *	MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
1 jermar 52
 */
53
 
54
/*
55
 * These variables either stay configured as initilalized, or are changed by
56
 * the MP configuration code.
57
 *
58
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
59
 * optimize the code too much and accesses to l_apic and io_apic, that must
60
 * always be 32-bit, would use byte oriented instructions.
61
 */
62
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
63
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
64
 
65
__u32 apic_id_mask = 0;
66
 
514 jermar 67
static int apic_poll_errors(void);
1 jermar 68
 
515 jermar 69
#ifdef LAPIC_VERBOSE
514 jermar 70
static char *delmod_str[] = {
71
	"Fixed",
72
	"Lowest Priority",
73
	"SMI",
74
	"Reserved",
75
	"NMI",
76
	"INIT",
77
	"STARTUP",
78
	"ExtInt"
79
};
80
 
81
static char *destmod_str[] = {
82
	"Physical",
83
	"Logical"
84
};
85
 
86
static char *trigmod_str[] = {
87
	"Edge",
88
	"Level"
89
};
90
 
91
static char *mask_str[] = {
92
	"Unmasked",
93
	"Masked"
94
};
95
 
96
static char *delivs_str[] = {
97
	"Idle",
98
	"Send Pending"
99
};
100
 
101
static char *tm_mode_str[] = {
102
	"One-shot",
103
	"Periodic"
104
};
105
 
106
static char *intpol_str[] = {
107
	"Polarity High",
108
	"Polarity Low"
109
};
515 jermar 110
#endif /* LAPIC_VERBOSE */
514 jermar 111
 
576 palkovsky 112
 
113
static void apic_spurious(int n, void *stack);
114
static void l_apic_timer_interrupt(int n, void *stack);
115
 
513 jermar 116
/** Initialize APIC on BSP. */
1 jermar 117
void apic_init(void)
118
{
515 jermar 119
	io_apic_id_t idreg;
120
	int i;
1 jermar 121
 
576 palkovsky 122
	exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);
1 jermar 123
 
124
	enable_irqs_function = io_apic_enable_irqs;
125
	disable_irqs_function = io_apic_disable_irqs;
126
	eoi_function = l_apic_eoi;
127
 
128
	/*
129
	 * Configure interrupt routing.
130
	 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
131
	 * Other interrupts will be forwarded to the lowest priority CPU.
132
	 */
133
	io_apic_disable_irqs(0xffff);
576 palkovsky 134
	exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);
515 jermar 135
	for (i = 0; i < IRQ_COUNT; i++) {
1 jermar 136
		int pin;
137
 
512 jermar 138
		if ((pin = smp_irq_to_pin(i)) != -1) {
515 jermar 139
			io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
512 jermar 140
		}
1 jermar 141
	}
142
 
143
	/*
144
	 * Ensure that io_apic has unique ID.
145
	 */
515 jermar 146
	idreg.value = io_apic_read(IOAPICID);
147
	if ((1<<idreg.apic_id) & apic_id_mask) {	/* see if IO APIC ID is used already */
148
		for (i = 0; i < APIC_ID_COUNT; i++) {
1 jermar 149
			if (!((1<<i) & apic_id_mask)) {
515 jermar 150
				idreg.apic_id = i;
151
				io_apic_write(IOAPICID, idreg.value);
1 jermar 152
				break;
153
			}
154
		}
155
	}
156
 
157
	/*
158
	 * Configure the BSP's lapic.
159
	 */
160
	l_apic_init();
515 jermar 161
 
1 jermar 162
	l_apic_debug();	
163
}
164
 
514 jermar 165
/** APIC spurious interrupt handler.
166
 *
167
 * @param n Interrupt vector.
168
 * @param stack Interrupted stack.
169
 */
576 palkovsky 170
void apic_spurious(int n, void *stack)
1 jermar 171
{
15 jermar 172
	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
1 jermar 173
}
174
 
514 jermar 175
/** Poll for APIC errors.
176
 *
177
 * Examine Error Status Register and report all errors found.
178
 *
179
 * @return 0 on error, 1 on success.
180
 */
1 jermar 181
int apic_poll_errors(void)
182
{
514 jermar 183
	esr_t esr;
1 jermar 184
 
514 jermar 185
	esr.value = l_apic[ESR];
1 jermar 186
 
514 jermar 187
	if (esr.send_checksum_error)
515 jermar 188
		printf("Send Checksum Error\n");
514 jermar 189
	if (esr.receive_checksum_error)
515 jermar 190
		printf("Receive Checksum Error\n");
514 jermar 191
	if (esr.send_accept_error)
1 jermar 192
		printf("Send Accept Error\n");
514 jermar 193
	if (esr.receive_accept_error)
1 jermar 194
		printf("Receive Accept Error\n");
514 jermar 195
	if (esr.send_illegal_vector)
1 jermar 196
		printf("Send Illegal Vector\n");
514 jermar 197
	if (esr.received_illegal_vector)
1 jermar 198
		printf("Received Illegal Vector\n");
514 jermar 199
	if (esr.illegal_register_address)
1 jermar 200
		printf("Illegal Register Address\n");
125 jermar 201
 
514 jermar 202
	return !esr.err_bitmap;
1 jermar 203
}
204
 
514 jermar 205
/** Send all CPUs excluding CPU IPI vector.
206
 *
207
 * @param vector Interrupt vector to be sent.
208
 *
209
 * @return 0 on failure, 1 on success.
5 jermar 210
 */
211
int l_apic_broadcast_custom_ipi(__u8 vector)
212
{
513 jermar 213
	icr_t icr;
5 jermar 214
 
513 jermar 215
	icr.lo = l_apic[ICRlo];
216
	icr.delmod = DELMOD_FIXED;
217
	icr.destmod = DESTMOD_LOGIC;
218
	icr.level = LEVEL_ASSERT;
219
	icr.shorthand = SHORTHAND_ALL_EXCL;
220
	icr.trigger_mode = TRIGMOD_LEVEL;
221
	icr.vector = vector;
5 jermar 222
 
513 jermar 223
	l_apic[ICRlo] = icr.lo;
5 jermar 224
 
513 jermar 225
	icr.lo = l_apic[ICRlo];
515 jermar 226
	if (icr.delivs == DELIVS_PENDING)
5 jermar 227
		printf("IPI is pending.\n");
228
 
229
	return apic_poll_errors();
230
}
231
 
514 jermar 232
/** Universal Start-up Algorithm for bringing up the AP processors.
233
 *
234
 * @param apicid APIC ID of the processor to be brought up.
235
 *
236
 * @return 0 on failure, 1 on success.
1 jermar 237
 */
238
int l_apic_send_init_ipi(__u8 apicid)
239
{
513 jermar 240
	icr_t icr;
1 jermar 241
	int i;
242
 
243
	/*
244
	 * Read the ICR register in and zero all non-reserved fields.
245
	 */
513 jermar 246
	icr.lo = l_apic[ICRlo];
247
	icr.hi = l_apic[ICRhi];
1 jermar 248
 
513 jermar 249
	icr.delmod = DELMOD_INIT;
250
	icr.destmod = DESTMOD_PHYS;
251
	icr.level = LEVEL_ASSERT;
252
	icr.trigger_mode = TRIGMOD_LEVEL;
253
	icr.shorthand = SHORTHAND_NONE;
254
	icr.vector = 0;
255
	icr.dest = apicid;
1 jermar 256
 
513 jermar 257
	l_apic[ICRhi] = icr.hi;
258
	l_apic[ICRlo] = icr.lo;
27 jermar 259
 
1 jermar 260
	/*
261
	 * According to MP Specification, 20us should be enough to
262
	 * deliver the IPI.
263
	 */
264
	delay(20);
265
 
266
	if (!apic_poll_errors()) return 0;
267
 
513 jermar 268
	icr.lo = l_apic[ICRlo];
515 jermar 269
	if (icr.delivs == DELIVS_PENDING)
1 jermar 270
		printf("IPI is pending.\n");
27 jermar 271
 
513 jermar 272
	icr.delmod = DELMOD_INIT;
273
	icr.destmod = DESTMOD_PHYS;
274
	icr.level = LEVEL_DEASSERT;
275
	icr.shorthand = SHORTHAND_NONE;
276
	icr.trigger_mode = TRIGMOD_LEVEL;
277
	icr.vector = 0;
278
	l_apic[ICRlo] = icr.lo;
1 jermar 279
 
280
	/*
281
	 * Wait 10ms as MP Specification specifies.
282
	 */
283
	delay(10000);
284
 
27 jermar 285
	if (!is_82489DX_apic(l_apic[LAVR])) {
286
		/*
287
		 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
288
		 */
289
		for (i = 0; i<2; i++) {
513 jermar 290
			icr.lo = l_apic[ICRlo];
291
			icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
292
			icr.delmod = DELMOD_STARTUP;
293
			icr.destmod = DESTMOD_PHYS;
294
			icr.level = LEVEL_ASSERT;
295
			icr.shorthand = SHORTHAND_NONE;
296
			icr.trigger_mode = TRIGMOD_LEVEL;
297
			l_apic[ICRlo] = icr.lo;
27 jermar 298
			delay(200);
299
		}
1 jermar 300
	}
301
 
302
	return apic_poll_errors();
303
}
304
 
514 jermar 305
/** Initialize Local APIC. */
1 jermar 306
void l_apic_init(void)
307
{
513 jermar 308
	lvt_error_t error;
309
	lvt_lint_t lint;
310
	svr_t svr;
514 jermar 311
	icr_t icr;
312
	tdcr_t tdcr;
513 jermar 313
	lvt_tm_t tm;
314
	__u32 t1, t2;
1 jermar 315
 
513 jermar 316
	/* Initialize LVT Error register. */
317
	error.value = l_apic[LVT_Err];
318
	error.masked = true;
319
	l_apic[LVT_Err] = error.value;
1 jermar 320
 
513 jermar 321
	/* Initialize LVT LINT0 register. */
322
	lint.value = l_apic[LVT_LINT0];
323
	lint.masked = true;
324
	l_apic[LVT_LINT0] = lint.value;
1 jermar 325
 
513 jermar 326
	/* Initialize LVT LINT1 register. */
327
	lint.value = l_apic[LVT_LINT1];
328
	lint.masked = true;
329
	l_apic[LVT_LINT1] = lint.value;
330
 
331
	/* Spurious-Interrupt Vector Register initialization. */
332
	svr.value = l_apic[SVR];
333
	svr.vector = VECTOR_APIC_SPUR;
334
	svr.lapic_enabled = true;
335
	l_apic[SVR] = svr.value;
336
 
1 jermar 337
	l_apic[TPR] &= TPRClear;
338
 
31 jermar 339
	if (CPU->arch.family >= 6)
340
		enable_l_apic_in_msr();
1 jermar 341
 
513 jermar 342
	/* Interrupt Command Register initialization. */
343
	icr.lo = l_apic[ICRlo];
344
	icr.delmod = DELMOD_INIT;
345
	icr.destmod = DESTMOD_PHYS;
346
	icr.level = LEVEL_DEASSERT;
347
	icr.shorthand = SHORTHAND_ALL_INCL;
348
	icr.trigger_mode = TRIGMOD_LEVEL;
349
	l_apic[ICRlo] = icr.lo;
1 jermar 350
 
514 jermar 351
	/* Timer Divide Configuration Register initialization. */
352
	tdcr.value = l_apic[TDCR];
353
	tdcr.div_value = DIVIDE_1;
354
	l_apic[TDCR] = tdcr.value;
1 jermar 355
 
514 jermar 356
	/* Program local timer. */
513 jermar 357
	tm.value = l_apic[LVT_Tm];
358
	tm.vector = VECTOR_CLK;
359
	tm.mode = TIMER_PERIODIC;
360
	tm.masked = false;
361
	l_apic[LVT_Tm] = tm.value;
362
 
514 jermar 363
	/* Measure and configure the timer to generate timer interrupt each ms. */
1 jermar 364
	t1 = l_apic[CCRT];
365
	l_apic[ICRT] = 0xffffffff;
366
 
367
	while (l_apic[CCRT] == t1)
368
		;
369
 
370
	t1 = l_apic[CCRT];
371
	delay(1000);
372
	t2 = l_apic[CCRT];
373
 
374
	l_apic[ICRT] = t1-t2;
375
}
376
 
514 jermar 377
/** Local APIC End of Interrupt. */
1 jermar 378
void l_apic_eoi(void)
379
{
380
	l_apic[EOI] = 0;
381
}
382
 
514 jermar 383
/** Dump content of Local APIC registers. */
1 jermar 384
void l_apic_debug(void)
385
{
386
#ifdef LAPIC_VERBOSE
514 jermar 387
	lvt_tm_t tm;
388
	lvt_lint_t lint;
389
	lvt_error_t error;	
390
 
16 jermar 391
	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
1 jermar 392
 
514 jermar 393
	tm.value = l_apic[LVT_Tm];
394
	printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
395
	lint.value = l_apic[LVT_LINT0];
396
	printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
397
	lint.value = l_apic[LVT_LINT1];	
398
	printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);	
399
	error.value = l_apic[LVT_Err];
400
	printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
1 jermar 401
#endif
402
}
403
 
514 jermar 404
/** Local APIC Timer Interrupt.
405
 *
406
 * @param n Interrupt vector number.
407
 * @param stack Interrupted stack.
408
 */
576 palkovsky 409
void l_apic_timer_interrupt(int n, void *stack)
1 jermar 410
{
411
	l_apic_eoi();
412
	clock();
413
}
414
 
514 jermar 415
/** Get Local APIC ID.
416
 *
417
 * @return Local APIC ID.
418
 */
81 jermar 419
__u8 l_apic_id(void)
16 jermar 420
{
515 jermar 421
	l_apic_id_t idreg;
514 jermar 422
 
515 jermar 423
	idreg.value = l_apic[L_APIC_ID];
424
	return idreg.apic_id;
16 jermar 425
}
426
 
514 jermar 427
/** Read from IO APIC register.
428
 *
429
 * @param address IO APIC register address.
430
 *
431
 * @return Content of the addressed IO APIC register.
432
 */
1 jermar 433
__u32 io_apic_read(__u8 address)
434
{
514 jermar 435
	io_regsel_t regsel;
1 jermar 436
 
514 jermar 437
	regsel.value = io_apic[IOREGSEL];
438
	regsel.reg_addr = address;
439
	io_apic[IOREGSEL] = regsel.value;
1 jermar 440
	return io_apic[IOWIN];
441
}
442
 
514 jermar 443
/** Write to IO APIC register.
444
 *
445
 * @param address IO APIC register address.
446
 * @param Content to be written to the addressed IO APIC register.
447
 */
1 jermar 448
void io_apic_write(__u8 address, __u32 x)
449
{
514 jermar 450
	io_regsel_t regsel;
451
 
452
	regsel.value = io_apic[IOREGSEL];
453
	regsel.reg_addr = address;
454
	io_apic[IOREGSEL] = regsel.value;
1 jermar 455
	io_apic[IOWIN] = x;
456
}
457
 
514 jermar 458
/** Change some attributes of one item in I/O Redirection Table.
459
 *
460
 * @param pin IO APIC pin number.
461
 * @param dest Interrupt destination address.
462
 * @param v Interrupt vector to trigger.
463
 * @param flags Flags.
464
 */
465
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
1 jermar 466
{
512 jermar 467
	io_redirection_reg_t reg;
514 jermar 468
	int dlvr = DELMOD_FIXED;
1 jermar 469
 
470
	if (flags & LOPRI)
512 jermar 471
		dlvr = DELMOD_LOWPRI;
472
 
1 jermar 473
 
514 jermar 474
	reg.lo = io_apic_read(IOREDTBL + pin*2);
475
	reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
1 jermar 476
 
512 jermar 477
	reg.dest =  dest;
478
	reg.destmod = DESTMOD_LOGIC;
479
	reg.trigger_mode = TRIGMOD_EDGE;
480
	reg.intpol = POLARITY_HIGH;
481
	reg.delmod = dlvr;
482
	reg.intvec = v;
1 jermar 483
 
514 jermar 484
	io_apic_write(IOREDTBL + pin*2, reg.lo);
485
	io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
1 jermar 486
}
487
 
514 jermar 488
/** Mask IRQs in IO APIC.
489
 *
490
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
491
 */
1 jermar 492
void io_apic_disable_irqs(__u16 irqmask)
493
{
512 jermar 494
	io_redirection_reg_t reg;
495
	int i, pin;
1 jermar 496
 
497
	for (i=0;i<16;i++) {
515 jermar 498
		if (irqmask & (1<<i)) {
1 jermar 499
			/*
500
			 * Mask the signal input in IO APIC if there is a
501
			 * mapping for the respective IRQ number.
502
			 */
512 jermar 503
			pin = smp_irq_to_pin(i);
1 jermar 504
			if (pin != -1) {
512 jermar 505
				reg.lo = io_apic_read(IOREDTBL + pin*2);
506
				reg.masked = true;
507
				io_apic_write(IOREDTBL + pin*2, reg.lo);
1 jermar 508
			}
509
 
510
		}
511
	}
512
}
513
 
514 jermar 514
/** Unmask IRQs in IO APIC.
515
 *
516
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
517
 */
1 jermar 518
void io_apic_enable_irqs(__u16 irqmask)
519
{
512 jermar 520
	int i, pin;
521
	io_redirection_reg_t reg;	
1 jermar 522
 
523
	for (i=0;i<16;i++) {
515 jermar 524
		if (irqmask & (1<<i)) {
1 jermar 525
			/*
526
			 * Unmask the signal input in IO APIC if there is a
527
			 * mapping for the respective IRQ number.
528
			 */
512 jermar 529
			pin = smp_irq_to_pin(i);
1 jermar 530
			if (pin != -1) {
512 jermar 531
				reg.lo = io_apic_read(IOREDTBL + pin*2);
532
				reg.masked = false;
533
				io_apic_write(IOREDTBL + pin*2, reg.lo);
1 jermar 534
			}
535
 
536
		}
537
	}
538
}
539
 
458 decky 540
#endif /* CONFIG_SMP */