Subversion Repositories HelenOS-historic

Rev

Rev 1289 | Rev 1702 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
1 jermar 1
/*
2
 * Copyright (C) 2001-2004 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
#include <arch/pm.h>
30
#include <config.h>
31
#include <arch/types.h>
32
#include <typedefs.h>
33
#include <arch/interrupt.h>
34
#include <arch/asm.h>
35
#include <arch/context.h>
36
#include <panic.h>
167 jermar 37
#include <arch/mm/page.h>
814 palkovsky 38
#include <mm/slab.h>
195 vana 39
#include <memstr.h>
244 decky 40
#include <arch/boot/boot.h>
576 palkovsky 41
#include <interrupt.h>
1 jermar 42
 
43
/*
11 jermar 44
 * Early ia32 configuration functions and data structures.
1 jermar 45
 */
46
 
47
/*
48
 * We have no use for segmentation so we set up flat mode. In this
49
 * mode, we use, for each privilege level, two segments spanning the
50
 * whole memory. One is for code and one is for data.
1112 palkovsky 51
 *
52
 * One is for GS register which holds pointer to the TLS thread
53
 * structure in it's base.
1 jermar 54
 */
1187 jermar 55
descriptor_t gdt[GDT_ITEMS] = {
125 jermar 56
	/* NULL descriptor */
57
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
58
	/* KTEXT descriptor */
59
	{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
60
	/* KDATA descriptor */
61
	{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
62
	/* UTEXT descriptor */
63
	{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
64
	/* UDATA descriptor */
65
	{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
66
	/* TSS descriptor - set up will be completed later */
1112 palkovsky 67
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1189 jermar 68
	/* TLS descriptor */
1287 vana 69
	{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
70
	/* VESA Init descriptor */
1292 vana 71
#ifdef CONFIG_FB
1289 vana 72
	{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 73
#endif	
1 jermar 74
};
75
 
1187 jermar 76
static idescriptor_t idt[IDT_ITEMS];
1 jermar 77
 
1187 jermar 78
static tss_t tss;
1 jermar 79
 
1187 jermar 80
tss_t *tss_p = NULL;
1 jermar 81
 
22 jermar 82
/* gdtr is changed by kmp before next CPU is initialized */
1187 jermar 83
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
84
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
1 jermar 85
 
1187 jermar 86
void gdt_setbase(descriptor_t *d, __address base)
1 jermar 87
{
125 jermar 88
	d->base_0_15 = base & 0xffff;
89
	d->base_16_23 = ((base) >> 16) & 0xff;
90
	d->base_24_31 = ((base) >> 24) & 0xff;
1 jermar 91
}
92
 
1187 jermar 93
void gdt_setlimit(descriptor_t *d, __u32 limit)
1 jermar 94
{
125 jermar 95
	d->limit_0_15 = limit & 0xffff;
96
	d->limit_16_19 = (limit >> 16) & 0xf;
1 jermar 97
}
98
 
1187 jermar 99
void idt_setoffset(idescriptor_t *d, __address offset)
1 jermar 100
{
112 jermar 101
	/*
102
	 * Offset is a linear address.
103
	 */
104
	d->offset_0_15 = offset & 0xffff;
105
	d->offset_16_31 = offset >> 16;
1 jermar 106
}
107
 
1187 jermar 108
void tss_initialize(tss_t *t)
1 jermar 109
{
110
	memsetb((__address) t, sizeof(struct tss), 0);
111
}
112
 
113
/*
114
 * This function takes care of proper setup of IDT and IDTR.
115
 */
116
void idt_init(void)
117
{
1187 jermar 118
	idescriptor_t *d;
1 jermar 119
	int i;
125 jermar 120
 
1 jermar 121
	for (i = 0; i < IDT_ITEMS; i++) {
122
		d = &idt[i];
123
 
124
		d->unused = 0;
125
		d->selector = selector(KTEXT_DES);
126
 
127
		d->access = AR_PRESENT | AR_INTERRUPT;	/* masking interrupt */
128
 
129
		if (i == VECTOR_SYSCALL) {
130
			/*
131
			 * The syscall interrupt gate must be calleable from userland.
132
			 */
133
			d->access |= DPL_USER;
134
		}
135
 
136
		idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
958 jermar 137
		exc_register(i, "undef", (iroutine) null_interrupt);
1 jermar 138
	}
958 jermar 139
	exc_register(13, "gp_fault", (iroutine) gp_fault);
140
	exc_register( 7, "nm_fault", (iroutine) nm_fault);
141
	exc_register(12, "ss_fault", (iroutine) ss_fault);
1019 vana 142
	exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
1 jermar 143
}
144
 
145
 
144 vana 146
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
141 vana 147
static void clean_IOPL_NT_flags(void)
148
{
1187 jermar 149
	__asm__ volatile (
150
		"pushfl\n"
151
		"pop %%eax\n"
152
		"and $0xffff8fff, %%eax\n"
153
		"push %%eax\n"
154
		"popfl\n"
155
		: : : "eax"
141 vana 156
	);
157
}
158
 
144 vana 159
/* Clean AM(18) flag in CR0 register */
143 vana 160
static void clean_AM_flag(void)
161
{
1187 jermar 162
	__asm__ volatile (
163
		"mov %%cr0, %%eax\n"
164
		"and $0xfffbffff, %%eax\n"
165
		"mov %%eax, %%cr0\n"
166
		: : : "eax"
143 vana 167
	);
168
}
141 vana 169
 
1 jermar 170
void pm_init(void)
171
{
1187 jermar 172
	descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
173
	ptr_16_32_t idtr;
1 jermar 174
 
175
	/*
232 jermar 176
	 * Update addresses in GDT and IDT to their virtual counterparts.
177
	 */
271 decky 178
	idtr.limit = sizeof(idt);
232 jermar 179
	idtr.base = (__address) idt;
1186 jermar 180
	gdtr_load(&gdtr);
181
	idtr_load(&idtr);
232 jermar 182
 
183
	/*
1 jermar 184
	 * Each CPU has its private GDT and TSS.
185
	 * All CPUs share one IDT.
186
	 */
187
 
188
	if (config.cpu_active == 1) {
189
		idt_init();
190
		/*
191
		 * NOTE: bootstrap CPU has statically allocated TSS, because
192
		 * the heap hasn't been initialized so far.
193
		 */
194
		tss_p = &tss;
195
	}
196
	else {
1187 jermar 197
		tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
1 jermar 198
		if (!tss_p)
68 decky 199
			panic("could not allocate TSS\n");
1 jermar 200
	}
201
 
202
	tss_initialize(tss_p);
203
 
204
	gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
205
	gdt_p[TSS_DES].special = 1;
1251 jermar 206
	gdt_p[TSS_DES].granularity = 0;
1 jermar 207
 
208
	gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
1251 jermar 209
	gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
1 jermar 210
 
211
	/*
212
	 * As of this moment, the current CPU has its own GDT pointing
213
	 * to its own TSS. We just need to load the TR register.
214
	 */
1186 jermar 215
	tr_load(selector(TSS_DES));
141 vana 216
 
1251 jermar 217
	clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
144 vana 218
	clean_AM_flag();          /* Disable alignment check */
1 jermar 219
}
1112 palkovsky 220
 
221
void set_tls_desc(__address tls)
222
{
1187 jermar 223
	ptr_16_32_t cpugdtr;
1188 jermar 224
	descriptor_t *gdt_p;
1112 palkovsky 225
 
1186 jermar 226
	gdtr_store(&cpugdtr);
1188 jermar 227
	gdt_p = (descriptor_t *) cpugdtr.base;
1112 palkovsky 228
	gdt_setbase(&gdt_p[TLS_DES], tls);
229
	/* Reload gdt register to update GS in CPU */
1186 jermar 230
	gdtr_load(&cpugdtr);
1112 palkovsky 231
}