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178 palkovsky 1
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
799 palkovsky 3
 * Copyright (C) 2005-2006 Ondrej Palkovsky
178 palkovsky 4
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1702 cejka 30
 /** @addtogroup amd64	
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 * @{
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 */
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/** @file
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 */
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178 palkovsky 36
#include <arch/pm.h>
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#include <arch/mm/page.h>
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <interrupt.h>
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#include <mm/as.h>
178 palkovsky 43
 
206 palkovsky 44
#include <config.h>
178 palkovsky 45
 
206 palkovsky 46
#include <memstr.h>
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#include <mm/slab.h>
206 palkovsky 48
#include <debug.h>
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178 palkovsky 50
/*
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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1187 jermar 56
descriptor_t gdt[GDT_ITEMS] = {
178 palkovsky 57
	/* NULL descriptor */
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	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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	/* KTEXT descriptor */
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	{ .limit_0_15  = 0xffff, 
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	  .base_0_15   = 0, 
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	  .base_16_23  = 0, 
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	  .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE , 
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	  .limit_16_19 = 0xf, 
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	  .available   = 0, 
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	  .longmode    = 1, 
188 palkovsky 67
	  .special     = 0,
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	  .granularity = 1, 
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	  .base_24_31  = 0 },
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	/* KDATA descriptor */
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	{ .limit_0_15  = 0xffff, 
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	  .base_0_15   = 0, 
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	  .base_16_23  = 0, 
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	  .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 
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	  .limit_16_19 = 0xf, 
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	  .available   = 0, 
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	  .longmode    = 0, 
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	  .special     = 0, 
188 palkovsky 79
	  .granularity = 1, 
178 palkovsky 80
	  .base_24_31  = 0 },
803 palkovsky 81
	/* UDATA descriptor */
178 palkovsky 82
	{ .limit_0_15  = 0xffff, 
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	  .base_0_15   = 0, 
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	  .base_16_23  = 0, 
803 palkovsky 85
	  .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 
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	  .limit_16_19 = 0xf, 
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	  .available   = 0, 
803 palkovsky 88
	  .longmode    = 0, 
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	  .special     = 1, 
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	  .granularity = 1, 
178 palkovsky 91
	  .base_24_31  = 0 },
803 palkovsky 92
	/* UTEXT descriptor */
178 palkovsky 93
	{ .limit_0_15  = 0xffff, 
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	  .base_0_15   = 0, 
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	  .base_16_23  = 0, 
803 palkovsky 96
	  .access      = AR_PRESENT | AR_CODE | DPL_USER, 
178 palkovsky 97
	  .limit_16_19 = 0xf, 
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	  .available   = 0, 
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	  .longmode    = 1, 
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	  .special     = 0, 
178 palkovsky 101
	  .granularity = 1, 
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	  .base_24_31  = 0 },
332 palkovsky 103
	/* KTEXT 32-bit protected, for protected mode before long mode */
188 palkovsky 104
	{ .limit_0_15  = 0xffff, 
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	  .base_0_15   = 0, 
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	  .base_16_23  = 0, 
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	  .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 
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	  .limit_16_19 = 0xf, 
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	  .available   = 0, 
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	  .longmode    = 0, 
277 palkovsky 111
	  .special     = 1,
188 palkovsky 112
	  .granularity = 1, 
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	  .base_24_31  = 0 },
206 palkovsky 114
	/* TSS descriptor - set up will be completed later,
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	 * on AMD64 it is 64-bit - 2 items in table */
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	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1289 vana 117
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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	/* VESA Init descriptor */
1292 vana 119
#ifdef CONFIG_FB	
1289 vana 120
	{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 121
#endif
178 palkovsky 122
};
123
 
1187 jermar 124
idescriptor_t idt[IDT_ITEMS];
178 palkovsky 125
 
1780 jermar 126
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };
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ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };
229 palkovsky 128
 
1187 jermar 129
static tss_t tss;
130
tss_t *tss_p = NULL;
178 palkovsky 131
 
1780 jermar 132
void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
206 palkovsky 133
{
1187 jermar 134
	tss_descriptor_t *td = (tss_descriptor_t *) d;
206 palkovsky 135
 
136
	td->base_0_15 = base & 0xffff;
137
	td->base_16_23 = ((base) >> 16) & 0xff;
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	td->base_24_31 = ((base) >> 24) & 0xff;
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	td->base_32_63 = ((base) >> 32);
140
}
141
 
1780 jermar 142
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
206 palkovsky 143
{
1187 jermar 144
	struct tss_descriptor *td = (tss_descriptor_t *) d;
206 palkovsky 145
 
146
	td->limit_0_15 = limit & 0xffff;
147
	td->limit_16_19 = (limit >> 16) & 0xf;
148
}
149
 
1780 jermar 150
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
206 palkovsky 151
{
152
	/*
153
	 * Offset is a linear address.
154
	 */
155
	d->offset_0_15 = offset & 0xffff;
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	d->offset_16_31 = offset >> 16 & 0xffff;
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	d->offset_32_63 = offset >> 32;
158
}
159
 
1187 jermar 160
void tss_initialize(tss_t *t)
206 palkovsky 161
{
1780 jermar 162
	memsetb((uintptr_t) t, sizeof(tss_t), 0);
206 palkovsky 163
}
164
 
165
/*
166
 * This function takes care of proper setup of IDT and IDTR.
167
 */
168
void idt_init(void)
169
{
1187 jermar 170
	idescriptor_t *d;
206 palkovsky 171
	int i;
172
 
173
	for (i = 0; i < IDT_ITEMS; i++) {
174
		d = &idt[i];
175
 
176
		d->unused = 0;
211 palkovsky 177
		d->selector = gdtselector(KTEXT_DES);
206 palkovsky 178
 
179
		d->present = 1;
180
		d->type = AR_INTERRUPT;	/* masking interrupt */
181
 
1780 jermar 182
		idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
799 palkovsky 183
		exc_register(i, "undef", (iroutine)null_interrupt);
206 palkovsky 184
	}
1051 jermar 185
 
576 palkovsky 186
	exc_register( 7, "nm_fault", nm_fault);
187
	exc_register(12, "ss_fault", ss_fault);
1051 jermar 188
	exc_register(13, "gp_fault", gp_fault);
1050 palkovsky 189
	exc_register(14, "ident_mapper", ident_page_fault);
206 palkovsky 190
}
191
 
799 palkovsky 192
/** Initialize segmentation - code/data/idt tables
193
 *
194
 */
206 palkovsky 195
void pm_init(void)
196
{
1187 jermar 197
	descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
198
	tss_descriptor_t *tss_desc;
206 palkovsky 199
 
200
	/*
201
	 * Each CPU has its private GDT and TSS.
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	 * All CPUs share one IDT.
203
	 */
204
 
205
	if (config.cpu_active == 1) {
206
		idt_init();
207
		/*
208
		 * NOTE: bootstrap CPU has statically allocated TSS, because
209
		 * the heap hasn't been initialized so far.
210
		 */
211
		tss_p = &tss;
212
	}
213
	else {
1252 palkovsky 214
		/* We are going to use malloc, which may return
215
		 * non boot-mapped pointer, initialize the CR3 register
216
		 * ahead of page_init */
1780 jermar 217
		write_cr3((uintptr_t) AS_KERNEL->page_table);
1252 palkovsky 218
 
1187 jermar 219
		tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
206 palkovsky 220
		if (!tss_p)
221
			panic("could not allocate TSS\n");
222
	}
223
 
224
	tss_initialize(tss_p);
225
 
1187 jermar 226
	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
208 palkovsky 227
	tss_desc->present = 1;
228
	tss_desc->type = AR_TSS;
229
	tss_desc->dpl = PL_KERNEL;
206 palkovsky 230
 
1780 jermar 231
	gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 232
	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
206 palkovsky 233
 
1186 jermar 234
	gdtr_load(&gdtr);
235
	idtr_load(&idtr);
206 palkovsky 236
	/*
237
	 * As of this moment, the current CPU has its own GDT pointing
238
	 * to its own TSS. We just need to load the TR register.
239
	 */
1186 jermar 240
	tr_load(gdtselector(TSS_DES));
206 palkovsky 241
}
1702 cejka 242
 
243
 /** @}
244
 */
245