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418 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
418 jermar 3
 * All rights reserved.
4
 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
9
 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
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 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1784 jermar 29
/** @addtogroup sparc64
1702 cejka 30
 * @{
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 */
32
/** @file
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 */
34
 
1784 jermar 35
#ifndef KERN_sparc64_ASM_H_
36
#define KERN_sparc64_ASM_H_
418 jermar 37
 
2089 decky 38
#include <arch/arch.h>
418 jermar 39
#include <arch/types.h>
2089 decky 40
#include <align.h>
650 jermar 41
#include <arch/register.h>
418 jermar 42
#include <config.h>
1885 jermar 43
#include <arch/stack.h>
418 jermar 44
 
650 jermar 45
/** Read Processor State register.
46
 *
47
 * @return Value of PSTATE register.
48
 */
1780 jermar 49
static inline uint64_t pstate_read(void)
650 jermar 50
{
1780 jermar 51
    uint64_t v;
650 jermar 52
 
2082 decky 53
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
650 jermar 54
 
55
    return v;
56
}
57
 
58
/** Write Processor State register.
59
 *
1708 jermar 60
 * @param v New value of PSTATE register.
650 jermar 61
 */
1780 jermar 62
static inline void pstate_write(uint64_t v)
650 jermar 63
{
2082 decky 64
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
650 jermar 65
}
66
 
658 jermar 67
/** Read TICK_compare Register.
68
 *
69
 * @return Value of TICK_comapre register.
70
 */
1780 jermar 71
static inline uint64_t tick_compare_read(void)
658 jermar 72
{
1780 jermar 73
    uint64_t v;
658 jermar 74
 
2082 decky 75
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
658 jermar 76
 
77
    return v;
78
}
650 jermar 79
 
658 jermar 80
/** Write TICK_compare Register.
81
 *
1708 jermar 82
 * @param v New value of TICK_comapre register.
658 jermar 83
 */
1780 jermar 84
static inline void tick_compare_write(uint64_t v)
658 jermar 85
{
2082 decky 86
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
658 jermar 87
}
88
 
89
/** Read TICK Register.
90
 *
91
 * @return Value of TICK register.
92
 */
1780 jermar 93
static inline uint64_t tick_read(void)
658 jermar 94
{
1780 jermar 95
    uint64_t v;
658 jermar 96
 
2082 decky 97
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
658 jermar 98
 
99
    return v;
100
}
101
 
102
/** Write TICK Register.
103
 *
1708 jermar 104
 * @param v New value of TICK register.
658 jermar 105
 */
1780 jermar 106
static inline void tick_write(uint64_t v)
658 jermar 107
{
2082 decky 108
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
658 jermar 109
}
110
 
1882 jermar 111
/** Read FPRS Register.
112
 *
113
 * @return Value of FPRS register.
114
 */
115
static inline uint64_t fprs_read(void)
116
{
117
    uint64_t v;
118
 
2082 decky 119
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
1882 jermar 120
 
121
    return v;
122
}
123
 
124
/** Write FPRS Register.
125
 *
126
 * @param v New value of FPRS register.
127
 */
128
static inline void fprs_write(uint64_t v)
129
{
2082 decky 130
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
1882 jermar 131
}
132
 
664 jermar 133
/** Read SOFTINT Register.
134
 *
135
 * @return Value of SOFTINT register.
136
 */
1780 jermar 137
static inline uint64_t softint_read(void)
664 jermar 138
{
1780 jermar 139
    uint64_t v;
658 jermar 140
 
2082 decky 141
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
664 jermar 142
 
143
    return v;
144
}
145
 
146
/** Write SOFTINT Register.
147
 *
1708 jermar 148
 * @param v New value of SOFTINT register.
664 jermar 149
 */
1780 jermar 150
static inline void softint_write(uint64_t v)
664 jermar 151
{
2082 decky 152
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
664 jermar 153
}
154
 
665 jermar 155
/** Write CLEAR_SOFTINT Register.
156
 *
157
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
158
 *
1708 jermar 159
 * @param v New value of CLEAR_SOFTINT register.
665 jermar 160
 */
1780 jermar 161
static inline void clear_softint_write(uint64_t v)
665 jermar 162
{
2082 decky 163
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
665 jermar 164
}
165
 
1849 jermar 166
/** Write SET_SOFTINT Register.
167
 *
168
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
169
 *
170
 * @param v New value of SET_SOFTINT register.
171
 */
172
static inline void set_softint_write(uint64_t v)
173
{
2082 decky 174
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
1849 jermar 175
}
176
 
418 jermar 177
/** Enable interrupts.
178
 *
179
 * Enable interrupts and return previous
180
 * value of IPL.
181
 *
182
 * @return Old interrupt priority level.
183
 */
184
static inline ipl_t interrupts_enable(void) {
650 jermar 185
    pstate_reg_t pstate;
1780 jermar 186
    uint64_t value;
650 jermar 187
 
188
    value = pstate_read();
189
    pstate.value = value;
190
    pstate.ie = true;
191
    pstate_write(pstate.value);
192
 
193
    return (ipl_t) value;
418 jermar 194
}
195
 
196
/** Disable interrupts.
197
 *
198
 * Disable interrupts and return previous
199
 * value of IPL.
200
 *
201
 * @return Old interrupt priority level.
202
 */
203
static inline ipl_t interrupts_disable(void) {
650 jermar 204
    pstate_reg_t pstate;
1780 jermar 205
    uint64_t value;
650 jermar 206
 
207
    value = pstate_read();
208
    pstate.value = value;
209
    pstate.ie = false;
210
    pstate_write(pstate.value);
211
 
212
    return (ipl_t) value;
418 jermar 213
}
214
 
215
/** Restore interrupt priority level.
216
 *
217
 * Restore IPL.
218
 *
219
 * @param ipl Saved interrupt priority level.
220
 */
221
static inline void interrupts_restore(ipl_t ipl) {
650 jermar 222
    pstate_reg_t pstate;
223
 
224
    pstate.value = pstate_read();
225
    pstate.ie = ((pstate_reg_t) ipl).ie;
226
    pstate_write(pstate.value);
418 jermar 227
}
228
 
229
/** Return interrupt priority level.
230
 *
231
 * Return IPL.
232
 *
233
 * @return Current interrupt priority level.
234
 */
235
static inline ipl_t interrupts_read(void) {
650 jermar 236
    return (ipl_t) pstate_read();
418 jermar 237
}
238
 
239
/** Return base address of current stack.
240
 *
241
 * Return the base address of the current stack.
242
 * The stack is assumed to be STACK_SIZE bytes long.
243
 * The stack must start on page boundary.
244
 */
1780 jermar 245
static inline uintptr_t get_stack_base(void)
418 jermar 246
{
1885 jermar 247
    uintptr_t unbiased_sp;
426 jermar 248
 
2082 decky 249
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
426 jermar 250
 
1885 jermar 251
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
418 jermar 252
}
253
 
640 jermar 254
/** Read Version Register.
255
 *
256
 * @return Value of VER register.
257
 */
1780 jermar 258
static inline uint64_t ver_read(void)
640 jermar 259
{
1780 jermar 260
    uint64_t v;
640 jermar 261
 
2082 decky 262
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
640 jermar 263
 
264
    return v;
265
}
266
 
2068 jermar 267
/** Read Trap Program Counter register.
529 jermar 268
 *
2068 jermar 269
 * @return Current value in TPC.
529 jermar 270
 */
2068 jermar 271
static inline uint64_t tpc_read(void)
529 jermar 272
{
1780 jermar 273
    uint64_t v;
529 jermar 274
 
2082 decky 275
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
529 jermar 276
 
277
    return v;
278
}
279
 
2068 jermar 280
/** Read Trap Level register.
873 jermar 281
 *
2068 jermar 282
 * @return Current value in TL.
873 jermar 283
 */
2068 jermar 284
static inline uint64_t tl_read(void)
873 jermar 285
{
1780 jermar 286
    uint64_t v;
873 jermar 287
 
2082 decky 288
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
873 jermar 289
 
290
    return v;
291
}
292
 
2068 jermar 293
/** Read Trap Base Address register.
883 jermar 294
 *
2068 jermar 295
 * @return Current value in TBA.
883 jermar 296
 */
2068 jermar 297
static inline uint64_t tba_read(void)
883 jermar 298
{
1780 jermar 299
    uint64_t v;
883 jermar 300
 
2082 decky 301
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
883 jermar 302
 
303
    return v;
304
}
873 jermar 305
 
529 jermar 306
/** Write Trap Base Address register.
307
 *
1708 jermar 308
 * @param v New value of TBA.
529 jermar 309
 */
1780 jermar 310
static inline void tba_write(uint64_t v)
529 jermar 311
{
2082 decky 312
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
529 jermar 313
}
314
 
1780 jermar 315
/** Load uint64_t from alternate space.
569 jermar 316
 *
317
 * @param asi ASI determining the alternate space.
318
 * @param va Virtual address within the ASI.
319
 *
320
 * @return Value read from the virtual address in the specified address space.
321
 */
1780 jermar 322
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
569 jermar 323
{
1780 jermar 324
    uint64_t v;
569 jermar 325
 
2082 decky 326
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
569 jermar 327
 
328
    return v;
329
}
529 jermar 330
 
1780 jermar 331
/** Store uint64_t to alternate space.
569 jermar 332
 *
333
 * @param asi ASI determining the alternate space.
334
 * @param va Virtual address within the ASI.
335
 * @param v Value to be written.
336
 */
1780 jermar 337
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
569 jermar 338
{
2082 decky 339
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
569 jermar 340
}
341
 
1855 jermar 342
/** Flush all valid register windows to memory. */
343
static inline void flushw(void)
344
{
2082 decky 345
    asm volatile ("flushw\n");
1855 jermar 346
}
347
 
1865 jermar 348
/** Switch to nucleus by setting TL to 1. */
349
static inline void nucleus_enter(void)
350
{
2082 decky 351
    asm volatile ("wrpr %g0, 1, %tl\n");
1865 jermar 352
}
353
 
354
/** Switch from nucleus by setting TL to 0. */
355
static inline void nucleus_leave(void)
356
{
2082 decky 357
    asm volatile ("wrpr %g0, %g0, %tl\n");
1865 jermar 358
}
359
 
1899 jermar 360
/** Read UPA_CONFIG register.
361
 *
362
 * @return Value of the UPA_CONFIG register.
363
 */
364
static inline uint64_t upa_config_read(void)
365
{
366
    return asi_u64_read(ASI_UPA_CONFIG, 0);
367
}
368
 
1856 jermar 369
extern void cpu_halt(void);
370
extern void cpu_sleep(void);
1881 jermar 371
extern void asm_delay_loop(const uint32_t usec);
418 jermar 372
 
1856 jermar 373
extern uint64_t read_from_ag_g7(void);
374
extern void write_to_ag_g6(uint64_t val);
375
extern void write_to_ag_g7(uint64_t val);
376
extern void write_to_ig_g6(uint64_t val);
377
 
1864 jermar 378
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
1860 jermar 379
 
418 jermar 380
#endif
1702 cejka 381
 
1784 jermar 382
/** @}
1702 cejka 383
 */