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| 1 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2001-2004 Jakub Jermar |
| 1 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 1888 | jermar | 29 | /** @addtogroup ia32 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1888 | jermar | 35 | #ifndef KERN_ia32_APIC_H_ |
| 36 | #define KERN_ia32_APIC_H_ |
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| 1 | jermar | 37 | |
| 38 | #include <arch/types.h> |
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| 39 | #include <cpu.h> |
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| 40 | |||
| 41 | #define FIXED (0<<0) |
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| 42 | #define LOPRI (1<<0) |
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| 43 | |||
| 515 | jermar | 44 | #define APIC_ID_COUNT 16 |
| 45 | |||
| 1 | jermar | 46 | /* local APIC macros */ |
| 47 | #define IPI_INIT 0 |
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| 48 | #define IPI_STARTUP 0 |
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| 49 | |||
| 513 | jermar | 50 | /** Delivery modes. */ |
| 51 | #define DELMOD_FIXED 0x0 |
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| 52 | #define DELMOD_LOWPRI 0x1 |
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| 53 | #define DELMOD_SMI 0x2 |
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| 54 | /* 0x3 reserved */ |
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| 55 | #define DELMOD_NMI 0x4 |
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| 56 | #define DELMOD_INIT 0x5 |
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| 57 | #define DELMOD_STARTUP 0x6 |
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| 58 | #define DELMOD_EXTINT 0x7 |
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| 1 | jermar | 59 | |
| 513 | jermar | 60 | /** Destination modes. */ |
| 61 | #define DESTMOD_PHYS 0x0 |
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| 62 | #define DESTMOD_LOGIC 0x1 |
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| 63 | |||
| 64 | /** Trigger Modes. */ |
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| 65 | #define TRIGMOD_EDGE 0x0 |
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| 66 | #define TRIGMOD_LEVEL 0x1 |
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| 67 | |||
| 68 | /** Levels. */ |
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| 69 | #define LEVEL_DEASSERT 0x0 |
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| 70 | #define LEVEL_ASSERT 0x1 |
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| 71 | |||
| 72 | /** Destination Shorthands. */ |
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| 73 | #define SHORTHAND_NONE 0x0 |
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| 74 | #define SHORTHAND_SELF 0x1 |
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| 75 | #define SHORTHAND_ALL_INCL 0x2 |
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| 76 | #define SHORTHAND_ALL_EXCL 0x3 |
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| 77 | |||
| 78 | /** Interrupt Input Pin Polarities. */ |
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| 79 | #define POLARITY_HIGH 0x0 |
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| 80 | #define POLARITY_LOW 0x1 |
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| 81 | |||
| 514 | jermar | 82 | /** Divide Values. (Bit 2 is always 0) */ |
| 83 | #define DIVIDE_2 0x0 |
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| 84 | #define DIVIDE_4 0x1 |
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| 85 | #define DIVIDE_8 0x2 |
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| 86 | #define DIVIDE_16 0x3 |
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| 87 | #define DIVIDE_32 0x8 |
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| 88 | #define DIVIDE_64 0x9 |
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| 89 | #define DIVIDE_128 0xa |
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| 90 | #define DIVIDE_1 0xb |
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| 91 | |||
| 92 | /** Timer Modes. */ |
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| 93 | #define TIMER_ONESHOT 0x0 |
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| 94 | #define TIMER_PERIODIC 0x1 |
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| 95 | |||
| 515 | jermar | 96 | /** Delivery status. */ |
| 97 | #define DELIVS_IDLE 0x0 |
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| 98 | #define DELIVS_PENDING 0x1 |
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| 1 | jermar | 99 | |
| 515 | jermar | 100 | /** Destination masks. */ |
| 101 | #define DEST_ALL 0xff |
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| 102 | |||
| 672 | jermar | 103 | /** Dest format models. */ |
| 104 | #define MODEL_FLAT 0xf |
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| 105 | #define MODEL_CLUSTER 0x0 |
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| 106 | |||
| 513 | jermar | 107 | /** Interrupt Command Register. */ |
| 1780 | jermar | 108 | #define ICRlo (0x300/sizeof(uint32_t)) |
| 109 | #define ICRhi (0x310/sizeof(uint32_t)) |
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| 2089 | decky | 110 | typedef struct { |
| 513 | jermar | 111 | union { |
| 1780 | jermar | 112 | uint32_t lo; |
| 513 | jermar | 113 | struct { |
| 1780 | jermar | 114 | uint8_t vector; /**< Interrupt Vector. */ |
| 513 | jermar | 115 | unsigned delmod : 3; /**< Delivery Mode. */ |
| 116 | unsigned destmod : 1; /**< Destination Mode. */ |
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| 117 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 118 | unsigned : 1; /**< Reserved. */ |
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| 119 | unsigned level : 1; /**< Level. */ |
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| 120 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 121 | unsigned : 2; /**< Reserved. */ |
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| 122 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
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| 123 | unsigned : 12; /**< Reserved. */ |
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| 124 | } __attribute__ ((packed)); |
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| 125 | }; |
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| 126 | union { |
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| 1780 | jermar | 127 | uint32_t hi; |
| 513 | jermar | 128 | struct { |
| 129 | unsigned : 24; /**< Reserved. */ |
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| 1780 | jermar | 130 | uint8_t dest; /**< Destination field. */ |
| 513 | jermar | 131 | } __attribute__ ((packed)); |
| 132 | }; |
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| 2089 | decky | 133 | } __attribute__ ((packed)) icr_t; |
| 1 | jermar | 134 | |
| 1251 | jermar | 135 | /* End Of Interrupt. */ |
| 1780 | jermar | 136 | #define EOI (0x0b0/sizeof(uint32_t)) |
| 1 | jermar | 137 | |
| 514 | jermar | 138 | /** Error Status Register. */ |
| 1780 | jermar | 139 | #define ESR (0x280/sizeof(uint32_t)) |
| 2089 | decky | 140 | typedef union { |
| 1780 | jermar | 141 | uint32_t value; |
| 142 | uint8_t err_bitmap; |
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| 514 | jermar | 143 | struct { |
| 144 | unsigned send_checksum_error : 1; |
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| 145 | unsigned receive_checksum_error : 1; |
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| 146 | unsigned send_accept_error : 1; |
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| 147 | unsigned receive_accept_error : 1; |
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| 148 | unsigned : 1; |
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| 149 | unsigned send_illegal_vector : 1; |
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| 150 | unsigned received_illegal_vector : 1; |
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| 151 | unsigned illegal_register_address : 1; |
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| 152 | unsigned : 24; |
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| 153 | } __attribute__ ((packed)); |
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| 2089 | decky | 154 | } esr_t; |
| 1 | jermar | 155 | |
| 156 | /* Task Priority Register */ |
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| 1780 | jermar | 157 | #define TPR (0x080/sizeof(uint32_t)) |
| 2089 | decky | 158 | typedef union { |
| 1780 | jermar | 159 | uint32_t value; |
| 750 | jermar | 160 | struct { |
| 161 | unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ |
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| 162 | unsigned pri : 4; /**< Task Priority. */ |
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| 163 | } __attribute__ ((packed)); |
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| 2089 | decky | 164 | } tpr_t; |
| 1 | jermar | 165 | |
| 513 | jermar | 166 | /** Spurious-Interrupt Vector Register. */ |
| 1780 | jermar | 167 | #define SVR (0x0f0/sizeof(uint32_t)) |
| 2089 | decky | 168 | typedef union { |
| 1780 | jermar | 169 | uint32_t value; |
| 513 | jermar | 170 | struct { |
| 1780 | jermar | 171 | uint8_t vector; /**< Spurious Vector. */ |
| 750 | jermar | 172 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ |
| 173 | unsigned focus_checking : 1; /**< Focus Processor Checking. */ |
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| 513 | jermar | 174 | unsigned : 22; /**< Reserved. */ |
| 175 | } __attribute__ ((packed)); |
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| 2089 | decky | 176 | } svr_t; |
| 1 | jermar | 177 | |
| 514 | jermar | 178 | /** Time Divide Configuration Register. */ |
| 1780 | jermar | 179 | #define TDCR (0x3e0/sizeof(uint32_t)) |
| 2089 | decky | 180 | typedef union { |
| 1780 | jermar | 181 | uint32_t value; |
| 514 | jermar | 182 | struct { |
| 183 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
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| 184 | unsigned : 28; /**< Reserved. */ |
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| 185 | } __attribute__ ((packed)); |
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| 2089 | decky | 186 | } tdcr_t; |
| 1 | jermar | 187 | |
| 188 | /* Initial Count Register for Timer */ |
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| 1780 | jermar | 189 | #define ICRT (0x380/sizeof(uint32_t)) |
| 1 | jermar | 190 | |
| 191 | /* Current Count Register for Timer */ |
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| 1780 | jermar | 192 | #define CCRT (0x390/sizeof(uint32_t)) |
| 1 | jermar | 193 | |
| 513 | jermar | 194 | /** LVT Timer register. */ |
| 1780 | jermar | 195 | #define LVT_Tm (0x320/sizeof(uint32_t)) |
| 2089 | decky | 196 | typedef union { |
| 1780 | jermar | 197 | uint32_t value; |
| 513 | jermar | 198 | struct { |
| 1780 | jermar | 199 | uint8_t vector; /**< Local Timer Interrupt vector. */ |
| 513 | jermar | 200 | unsigned : 4; /**< Reserved. */ |
| 201 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 202 | unsigned : 3; /**< Reserved. */ |
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| 203 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 204 | unsigned mode : 1; /**< Timer Mode. */ |
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| 205 | unsigned : 14; /**< Reserved. */ |
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| 206 | } __attribute__ ((packed)); |
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| 2089 | decky | 207 | } lvt_tm_t; |
| 513 | jermar | 208 | |
| 209 | /** LVT LINT registers. */ |
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| 1780 | jermar | 210 | #define LVT_LINT0 (0x350/sizeof(uint32_t)) |
| 211 | #define LVT_LINT1 (0x360/sizeof(uint32_t)) |
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| 2089 | decky | 212 | typedef union { |
| 1780 | jermar | 213 | uint32_t value; |
| 513 | jermar | 214 | struct { |
| 1780 | jermar | 215 | uint8_t vector; /**< LINT Interrupt vector. */ |
| 513 | jermar | 216 | unsigned delmod : 3; /**< Delivery Mode. */ |
| 217 | unsigned : 1; /**< Reserved. */ |
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| 218 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 219 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 220 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 221 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 222 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 223 | unsigned : 15; /**< Reserved. */ |
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| 224 | } __attribute__ ((packed)); |
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| 2089 | decky | 225 | } lvt_lint_t; |
| 513 | jermar | 226 | |
| 227 | /** LVT Error register. */ |
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| 1780 | jermar | 228 | #define LVT_Err (0x370/sizeof(uint32_t)) |
| 2089 | decky | 229 | typedef union { |
| 1780 | jermar | 230 | uint32_t value; |
| 513 | jermar | 231 | struct { |
| 1780 | jermar | 232 | uint8_t vector; /**< Local Timer Interrupt vector. */ |
| 513 | jermar | 233 | unsigned : 4; /**< Reserved. */ |
| 234 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 235 | unsigned : 3; /**< Reserved. */ |
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| 236 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 237 | unsigned : 15; /**< Reserved. */ |
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| 238 | } __attribute__ ((packed)); |
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| 2089 | decky | 239 | } lvt_error_t; |
| 513 | jermar | 240 | |
| 514 | jermar | 241 | /** Local APIC ID Register. */ |
| 1780 | jermar | 242 | #define L_APIC_ID (0x020/sizeof(uint32_t)) |
| 2089 | decky | 243 | typedef union { |
| 1780 | jermar | 244 | uint32_t value; |
| 514 | jermar | 245 | struct { |
| 246 | unsigned : 24; /**< Reserved. */ |
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| 1780 | jermar | 247 | uint8_t apic_id; /**< Local APIC ID. */ |
| 514 | jermar | 248 | } __attribute__ ((packed)); |
| 2089 | decky | 249 | } l_apic_id_t; |
| 1 | jermar | 250 | |
| 1251 | jermar | 251 | /** Local APIC Version Register */ |
| 1780 | jermar | 252 | #define LAVR (0x030/sizeof(uint32_t)) |
| 27 | jermar | 253 | #define LAVR_Mask 0xff |
| 254 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
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| 255 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
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| 256 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
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| 257 | |||
| 672 | jermar | 258 | /** Logical Destination Register. */ |
| 1780 | jermar | 259 | #define LDR (0x0d0/sizeof(uint32_t)) |
| 2089 | decky | 260 | typedef union { |
| 1780 | jermar | 261 | uint32_t value; |
| 672 | jermar | 262 | struct { |
| 1251 | jermar | 263 | unsigned : 24; /**< Reserved. */ |
| 1780 | jermar | 264 | uint8_t id; /**< Logical APIC ID. */ |
| 672 | jermar | 265 | } __attribute__ ((packed)); |
| 2089 | decky | 266 | } ldr_t; |
| 672 | jermar | 267 | |
| 268 | /** Destination Format Register. */ |
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| 1780 | jermar | 269 | #define DFR (0x0e0/sizeof(uint32_t)) |
| 2089 | decky | 270 | typedef union { |
| 1780 | jermar | 271 | uint32_t value; |
| 672 | jermar | 272 | struct { |
| 273 | unsigned : 28; /**< Reserved, all ones. */ |
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| 274 | unsigned model : 4; /**< Model. */ |
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| 275 | } __attribute__ ((packed)); |
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| 2089 | decky | 276 | } dfr_t; |
| 672 | jermar | 277 | |
| 1 | jermar | 278 | /* IO APIC */ |
| 1780 | jermar | 279 | #define IOREGSEL (0x00/sizeof(uint32_t)) |
| 280 | #define IOWIN (0x10/sizeof(uint32_t)) |
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| 1 | jermar | 281 | |
| 282 | #define IOAPICID 0x00 |
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| 283 | #define IOAPICVER 0x01 |
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| 284 | #define IOAPICARB 0x02 |
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| 285 | #define IOREDTBL 0x10 |
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| 286 | |||
| 514 | jermar | 287 | /** I/O Register Select Register. */ |
| 2089 | decky | 288 | typedef union { |
| 1780 | jermar | 289 | uint32_t value; |
| 514 | jermar | 290 | struct { |
| 1780 | jermar | 291 | uint8_t reg_addr; /**< APIC Register Address. */ |
| 514 | jermar | 292 | unsigned : 24; /**< Reserved. */ |
| 293 | } __attribute__ ((packed)); |
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| 2089 | decky | 294 | } io_regsel_t; |
| 514 | jermar | 295 | |
| 512 | jermar | 296 | /** I/O Redirection Register. */ |
| 2089 | decky | 297 | typedef struct io_redirection_reg { |
| 512 | jermar | 298 | union { |
| 1780 | jermar | 299 | uint32_t lo; |
| 512 | jermar | 300 | struct { |
| 1780 | jermar | 301 | uint8_t intvec; /**< Interrupt Vector. */ |
| 512 | jermar | 302 | unsigned delmod : 3; /**< Delivery Mode. */ |
| 303 | unsigned destmod : 1; /**< Destination mode. */ |
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| 304 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 305 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 306 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 307 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 308 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 309 | unsigned : 15; /**< Reserved. */ |
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| 513 | jermar | 310 | } __attribute__ ((packed)); |
| 512 | jermar | 311 | }; |
| 312 | union { |
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| 1780 | jermar | 313 | uint32_t hi; |
| 512 | jermar | 314 | struct { |
| 315 | unsigned : 24; /**< Reserved. */ |
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| 1780 | jermar | 316 | uint8_t dest : 8; /**< Destination Field. */ |
| 513 | jermar | 317 | } __attribute__ ((packed)); |
| 512 | jermar | 318 | }; |
| 319 | |||
| 2089 | decky | 320 | } __attribute__ ((packed)) io_redirection_reg_t; |
| 512 | jermar | 321 | |
| 515 | jermar | 322 | |
| 323 | /** IO APIC Identification Register. */ |
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| 2089 | decky | 324 | typedef union { |
| 1780 | jermar | 325 | uint32_t value; |
| 515 | jermar | 326 | struct { |
| 327 | unsigned : 24; /**< Reserved. */ |
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| 328 | unsigned apic_id : 4; /**< IO APIC ID. */ |
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| 329 | unsigned : 4; /**< Reserved. */ |
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| 330 | } __attribute__ ((packed)); |
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| 2089 | decky | 331 | } io_apic_id_t; |
| 515 | jermar | 332 | |
| 1780 | jermar | 333 | extern volatile uint32_t *l_apic; |
| 334 | extern volatile uint32_t *io_apic; |
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| 1 | jermar | 335 | |
| 1780 | jermar | 336 | extern uint32_t apic_id_mask; |
| 1 | jermar | 337 | |
| 338 | extern void apic_init(void); |
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| 339 | |||
| 340 | extern void l_apic_init(void); |
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| 341 | extern void l_apic_eoi(void); |
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| 1780 | jermar | 342 | extern int l_apic_broadcast_custom_ipi(uint8_t vector); |
| 343 | extern int l_apic_send_init_ipi(uint8_t apicid); |
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| 1 | jermar | 344 | extern void l_apic_debug(void); |
| 1780 | jermar | 345 | extern uint8_t l_apic_id(void); |
| 1 | jermar | 346 | |
| 1780 | jermar | 347 | extern uint32_t io_apic_read(uint8_t address); |
| 348 | extern void io_apic_write(uint8_t address , uint32_t x); |
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| 2441 | decky | 349 | extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags); |
| 1780 | jermar | 350 | extern void io_apic_disable_irqs(uint16_t irqmask); |
| 351 | extern void io_apic_enable_irqs(uint16_t irqmask); |
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| 1 | jermar | 352 | |
| 353 | #endif |
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| 1702 | cejka | 354 | |
| 1888 | jermar | 355 | /** @} |
| 1702 | cejka | 356 | */ |