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| Rev | Author | Line No. | Line |
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| 153 | jermar | 1 | /* |
| 2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
| 153 | jermar | 3 | * All rights reserved. |
| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 4377 | svoboda | 29 | /** @addtogroup ia32 |
| 1702 | cejka | 30 | * @{ |
| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 1888 | jermar | 35 | #ifndef KERN_ia32_BARRIER_H_ |
| 36 | #define KERN_ia32_BARRIER_H_ |
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| 153 | jermar | 37 | |
| 38 | /* |
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| 39 | * NOTE: |
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| 40 | * No barriers for critical section (i.e. spinlock) on IA-32 are needed: |
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| 41 | * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction |
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| 42 | * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers |
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| 43 | */ |
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| 44 | |||
| 45 | /* |
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| 46 | * Provisions are made to prevent compiler from reordering instructions itself. |
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| 47 | */ |
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| 48 | |||
| 4377 | svoboda | 49 | #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
| 50 | #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
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| 153 | jermar | 51 | |
| 469 | jermar | 52 | static inline void cpuid_serialization(void) |
| 53 | { |
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| 2082 | decky | 54 | asm volatile ( |
| 469 | jermar | 55 | "xorl %%eax, %%eax\n" |
| 56 | "cpuid\n" |
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| 57 | ::: "eax", "ebx", "ecx", "edx", "memory" |
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| 58 | ); |
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| 59 | } |
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| 60 | |||
| 4377 | svoboda | 61 | #if defined(CONFIG_FENCES_P4) |
| 62 | #define memory_barrier() asm volatile ("mfence\n" ::: "memory") |
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| 63 | #define read_barrier() asm volatile ("lfence\n" ::: "memory") |
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| 64 | #ifdef CONFIG_WEAK_MEMORY |
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| 65 | #define write_barrier() asm volatile ("sfence\n" ::: "memory") |
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| 66 | #else |
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| 67 | #define write_barrier() asm volatile ("" ::: "memory"); |
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| 68 | #endif |
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| 69 | #elif defined(CONFIG_FENCES_P3) |
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| 70 | #define memory_barrier() cpuid_serialization() |
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| 71 | #define read_barrier() cpuid_serialization() |
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| 72 | #ifdef CONFIG_WEAK_MEMORY |
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| 73 | #define write_barrier() asm volatile ("sfence\n" ::: "memory") |
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| 74 | #else |
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| 75 | #define write_barrier() asm volatile ("" ::: "memory"); |
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| 76 | #endif |
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| 469 | jermar | 77 | #else |
| 4377 | svoboda | 78 | #define memory_barrier() cpuid_serialization() |
| 79 | #define read_barrier() cpuid_serialization() |
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| 80 | #ifdef CONFIG_WEAK_MEMORY |
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| 81 | #define write_barrier() cpuid_serialization() |
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| 82 | #else |
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| 83 | #define write_barrier() asm volatile ("" ::: "memory"); |
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| 84 | #endif |
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| 153 | jermar | 85 | #endif |
| 423 | decky | 86 | |
| 3424 | svoboda | 87 | /* |
| 88 | * On ia32, the hardware takes care about instruction and data cache coherence, |
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| 89 | * even on SMP systems. We issue a write barrier to be sure that writes |
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| 90 | * queueing in the store buffer drain to the memory (even though it would be |
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| 91 | * sufficient for them to drain to the D-cache). |
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| 92 | */ |
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| 4377 | svoboda | 93 | #define smc_coherence(a) write_barrier() |
| 94 | #define smc_coherence_block(a, l) write_barrier() |
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| 3424 | svoboda | 95 | |
| 423 | decky | 96 | #endif |
| 1702 | cejka | 97 | |
| 1888 | jermar | 98 | /** @} |
| 1702 | cejka | 99 | */ |