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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2726 | vana | 1 | #ifndef _PCI22_H |
| 2 | #define _PCI22_H |
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| 3 | |||
| 4 | /*++ |
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| 5 | |||
| 6 | Copyright (c) 1999 Intel Corporation |
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| 7 | |||
| 8 | Module Name: |
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| 9 | |||
| 10 | pci22.h |
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| 11 | |||
| 12 | Abstract: |
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| 13 | Support for PCI 2.2 standard. |
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| 14 | |||
| 15 | |||
| 16 | |||
| 17 | |||
| 18 | Revision History |
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| 19 | |||
| 20 | --*/ |
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| 21 | |||
| 22 | #ifdef SOFT_SDV |
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| 23 | #define PCI_MAX_BUS 1 |
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| 24 | #else |
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| 25 | #define PCI_MAX_BUS 255 |
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| 26 | #endif |
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| 27 | |||
| 28 | #define PCI_MAX_DEVICE 31 |
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| 29 | #define PCI_MAX_FUNC 7 |
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| 30 | |||
| 31 | // |
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| 32 | // Command |
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| 33 | // |
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| 34 | #define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20 |
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| 35 | |||
| 36 | #pragma pack(1) |
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| 37 | typedef struct { |
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| 38 | UINT16 VendorId; |
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| 39 | UINT16 DeviceId; |
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| 40 | UINT16 Command; |
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| 41 | UINT16 Status; |
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| 42 | UINT8 RevisionID; |
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| 43 | UINT8 ClassCode[3]; |
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| 44 | UINT8 CacheLineSize; |
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| 45 | UINT8 LaytencyTimer; |
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| 46 | UINT8 HeaderType; |
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| 47 | UINT8 BIST; |
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| 48 | } PCI_DEVICE_INDEPENDENT_REGION; |
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| 49 | |||
| 50 | typedef struct { |
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| 51 | UINT32 Bar[6]; |
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| 52 | UINT32 CISPtr; |
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| 53 | UINT16 SubsystemVendorID; |
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| 54 | UINT16 SubsystemID; |
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| 55 | UINT32 ExpansionRomBar; |
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| 56 | UINT32 Reserved[2]; |
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| 57 | UINT8 InterruptLine; |
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| 58 | UINT8 InterruptPin; |
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| 59 | UINT8 MinGnt; |
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| 60 | UINT8 MaxLat; |
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| 61 | } PCI_DEVICE_HEADER_TYPE_REGION; |
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| 62 | |||
| 63 | typedef struct { |
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| 64 | PCI_DEVICE_INDEPENDENT_REGION Hdr; |
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| 65 | PCI_DEVICE_HEADER_TYPE_REGION Device; |
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| 66 | } PCI_TYPE00; |
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| 67 | |||
| 68 | typedef struct { |
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| 69 | UINT32 Bar[2]; |
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| 70 | UINT8 PrimaryBus; |
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| 71 | UINT8 SecondaryBus; |
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| 72 | UINT8 SubordinateBus; |
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| 73 | UINT8 SecondaryLatencyTimer; |
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| 74 | UINT8 IoBase; |
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| 75 | UINT8 IoLimit; |
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| 76 | UINT16 SecondaryStatus; |
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| 77 | UINT16 MemoryBase; |
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| 78 | UINT16 MemoryLimit; |
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| 79 | UINT16 PrefetchableMemoryBase; |
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| 80 | UINT16 PrefetchableMemoryLimit; |
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| 81 | UINT32 PrefetchableBaseUpper32; |
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| 82 | UINT32 PrefetchableLimitUpper32; |
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| 83 | UINT16 IoBaseUpper16; |
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| 84 | UINT16 IoLimitUpper16; |
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| 85 | UINT32 Reserved; |
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| 86 | UINT32 ExpansionRomBAR; |
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| 87 | UINT8 InterruptLine; |
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| 88 | UINT8 InterruptPin; |
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| 89 | UINT16 BridgeControl; |
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| 90 | } PCI_BRIDGE_CONTROL_REGISTER; |
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| 91 | |||
| 92 | #define PCI_CLASS_DISPLAY_CTRL 0x03 |
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| 93 | #define PCI_CLASS_VGA 0x00 |
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| 94 | |||
| 95 | #define PCI_CLASS_BRIDGE 0x06 |
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| 96 | #define PCI_CLASS_ISA 0x01 |
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| 97 | #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 |
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| 98 | |||
| 99 | #define PCI_CLASS_NETWORK 0x02 |
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| 100 | #define PCI_CLASS_ETHERNET 0x00 |
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| 101 | |||
| 102 | #define HEADER_TYPE_DEVICE 0x00 |
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| 103 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01 |
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| 104 | #define HEADER_TYPE_MULTI_FUNCTION 0x80 |
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| 105 | #define HEADER_LAYOUT_CODE 0x7f |
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| 106 | |||
| 107 | #define IS_PCI_BRIDGE(_p) ((((_p)->Hdr.HeaderType) & HEADER_LAYOUT_CODE) == HEADER_TYPE_PCI_TO_PCI_BRIDGE) |
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| 108 | #define IS_PCI_MULTI_FUNC(_p) (((_p)->Hdr.HeaderType) & HEADER_TYPE_MULTI_FUNCTION) |
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| 109 | |||
| 110 | typedef struct { |
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| 111 | PCI_DEVICE_INDEPENDENT_REGION Hdr; |
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| 112 | PCI_BRIDGE_CONTROL_REGISTER Bridge; |
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| 113 | } PCI_TYPE01; |
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| 114 | |||
| 115 | typedef struct { |
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| 116 | UINT8 Register; |
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| 117 | UINT8 Function; |
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| 118 | UINT8 Device; |
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| 119 | UINT8 Bus; |
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| 120 | UINT8 Reserved[4]; |
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| 121 | } DEFIO_PCI_ADDR; |
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| 122 | |||
| 123 | typedef struct { |
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| 124 | UINT32 Reg : 8; |
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| 125 | UINT32 Func : 3; |
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| 126 | UINT32 Dev : 5; |
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| 127 | UINT32 Bus : 8; |
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| 128 | UINT32 Reserved: 7; |
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| 129 | UINT32 Enable : 1; |
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| 130 | } PCI_CONFIG_ACCESS_CF8; |
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| 131 | |||
| 132 | #pragma pack() |
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| 133 | |||
| 134 | #define EFI_ROOT_BRIDGE_LIST 'eprb' |
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| 135 | typedef struct { |
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| 136 | UINTN Signature; |
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| 137 | |||
| 138 | UINT16 BridgeNumber; |
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| 139 | UINT16 PrimaryBus; |
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| 140 | UINT16 SubordinateBus; |
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| 141 | |||
| 142 | EFI_DEVICE_PATH *DevicePath; |
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| 143 | |||
| 144 | LIST_ENTRY Link; |
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| 145 | } PCI_ROOT_BRIDGE_ENTRY; |
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| 146 | |||
| 147 | |||
| 148 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55 |
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| 149 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 |
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| 150 | #define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32('P','C','I','R') |
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| 151 | |||
| 152 | #pragma pack(1) |
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| 153 | typedef struct { |
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| 154 | UINT16 Signature; // 0xaa55 |
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| 155 | UINT8 Reserved[0x16]; |
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| 156 | UINT16 PcirOffset; |
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| 157 | } PCI_EXPANSION_ROM_HEADER; |
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| 158 | |||
| 159 | |||
| 160 | typedef struct { |
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| 161 | UINT16 Signature; // 0xaa55 |
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| 162 | UINT16 InitializationSize; |
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| 163 | UINT16 EfiSignature; // 0x0EF1 |
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| 164 | UINT16 EfiSubsystem; |
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| 165 | UINT16 EfiMachineType; |
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| 166 | UINT8 Reserved[0x0A]; |
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| 167 | UINT16 EfiImageHeaderOffset; |
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| 168 | UINT16 PcirOffset; |
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| 169 | } EFI_PCI_EXPANSION_ROM_HEADER; |
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| 170 | |||
| 171 | typedef struct { |
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| 172 | UINT32 Signature; // "PCIR" |
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| 173 | UINT16 VendorId; |
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| 174 | UINT16 DeviceId; |
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| 175 | UINT16 Reserved0; |
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| 176 | UINT16 Length; |
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| 177 | UINT8 Revision; |
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| 178 | UINT8 ClassCode[3]; |
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| 179 | UINT16 ImageLength; |
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| 180 | UINT16 CodeRevision; |
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| 181 | UINT8 CodeType; |
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| 182 | UINT8 Indicator; |
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| 183 | UINT16 Reserved1; |
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| 184 | } PCI_DATA_STRUCTURE; |
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| 185 | #pragma pack() |
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| 186 | |||
| 187 | #endif |
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| 188 | |||
| 189 | |||
| 190 | |||
| 191 | |||
| 192 | |||
| 193 |