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| Rev | Author | Line No. | Line |
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| 3657 | vana | 1 | /* |
| 2 | * Copyright (c) 2005 Jakub Jermar, Jakub Vana |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /** @addtogroup ia64 |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | /** @file |
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| 33 | */ |
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| 34 | |||
| 35 | #ifndef LIBC_ia64_DDI_H_ |
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| 36 | #define LIBC_ia64_DDI_H_ |
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| 37 | |||
| 38 | #include <libarch/types.h> |
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| 39 | |||
| 40 | typedef uint64_t ioport_t; |
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| 41 | |||
| 42 | uint64_t get_ia64_iospace_address(void); |
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| 43 | |||
| 44 | extern uint64_t ia64_iospace_address; |
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| 45 | |||
| 46 | #define IA64_IOSPACE_ADDRESS (ia64_iospace_address?ia64_iospace_address:(ia64_iospace_address=get_ia64_iospace_address())) |
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| 47 | |||
| 48 | static inline void outb(ioport_t port,uint8_t v) |
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| 49 | { |
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| 50 | *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
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| 51 | |||
| 52 | asm volatile ("mf\n" ::: "memory"); |
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| 53 | } |
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| 54 | |||
| 55 | static inline void outw(ioport_t port,uint16_t v) |
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| 56 | { |
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| 57 | *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
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| 58 | |||
| 59 | asm volatile ("mf\n" ::: "memory"); |
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| 60 | } |
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| 61 | |||
| 62 | static inline void outl(ioport_t port,uint32_t v) |
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| 63 | { |
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| 64 | *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v; |
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| 65 | |||
| 66 | asm volatile ("mf\n" ::: "memory"); |
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| 67 | } |
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| 68 | |||
| 69 | |||
| 70 | |||
| 71 | static inline uint8_t inb(ioport_t port) |
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| 72 | { |
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| 73 | asm volatile ("mf\n" ::: "memory"); |
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| 74 | |||
| 75 | return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); |
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| 76 | } |
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| 77 | |||
| 78 | static inline uint16_t inw(ioport_t port) |
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| 79 | { |
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| 80 | asm volatile ("mf\n" ::: "memory"); |
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| 81 | |||
| 82 | return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 )))); |
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| 83 | } |
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| 84 | |||
| 85 | static inline uint32_t inl(ioport_t port) |
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| 86 | { |
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| 87 | asm volatile ("mf\n" ::: "memory"); |
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| 88 | |||
| 89 | return *((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))); |
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| 90 | } |
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| 91 | |||
| 92 | |||
| 93 | |||
| 94 | |||
| 95 | #endif |
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| 96 | |||
| 97 | /** @} |
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| 98 | */ |