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3743 | rimsky | 1 | /* |
2 | * Copyright (c) 2006 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup sparc64interrupt |
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30 | * @{ |
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31 | */ |
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32 | /** |
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33 | * @file |
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34 | * @brief This file contains fast MMU trap handlers. |
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35 | */ |
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36 | |||
37 | #ifndef KERN_sparc64_sun4u_MMU_TRAP_H_ |
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38 | #define KERN_sparc64_sun4u_MMU_TRAP_H_ |
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39 | |||
40 | #include <arch/stack.h> |
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41 | #include <arch/sun4u/regdef.h> |
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42 | #include <arch/mm/tlb.h> |
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43 | #include <arch/mm/sun4u/tlb.h> |
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44 | #include <arch/mm/sun4u/mmu.h> |
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45 | #include <arch/mm/sun4u/tte.h> |
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46 | #include <arch/trap/regwin.h> |
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47 | #include <arch/sun4u/arch.h> |
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48 | |||
49 | #ifdef CONFIG_TSB |
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50 | #include <arch/mm/tsb.h> |
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51 | #endif |
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52 | |||
53 | #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
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54 | #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
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55 | #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c |
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56 | |||
57 | #define FAST_MMU_HANDLER_SIZE 128 |
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58 | |||
59 | #ifdef __ASM__ |
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60 | |||
61 | .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
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62 | /* |
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63 | * First, try to refill TLB from TSB. |
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64 | */ |
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65 | #ifdef CONFIG_TSB |
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66 | ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register |
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67 | ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer |
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68 | ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 |
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69 | cmp %g1, %g4 ! is this the entry we are looking for? |
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70 | bne,pn %xcc, 0f |
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71 | nop |
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72 | stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB |
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73 | retry |
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74 | |||
75 | #endif |
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76 | 0: |
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77 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
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78 | PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
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79 | .endm |
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80 | |||
81 | .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl |
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82 | /* |
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83 | * First, try to refill TLB from TSB. |
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84 | */ |
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85 | |||
86 | #ifdef CONFIG_TSB |
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87 | ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register |
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88 | srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? |
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89 | brz,pn %g2, 0f |
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90 | ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer |
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91 | ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 |
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92 | cmp %g1, %g4 ! is this the entry we are looking for? |
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93 | bne,pn %xcc, 0f |
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94 | nop |
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95 | stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB |
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96 | retry |
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97 | #endif |
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98 | |||
99 | /* |
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100 | * Second, test if it is the portion of the kernel address space |
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101 | * which is faulting. If that is the case, immediately create |
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102 | * identity mapping for that page in DTLB. VPN 0 is excluded from |
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103 | * this treatment. |
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104 | * |
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105 | * Note that branch-delay slots are used in order to save space. |
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106 | */ |
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107 | 0: |
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108 | mov VA_DMMU_TAG_ACCESS, %g1 |
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109 | ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
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110 | set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
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111 | andcc %g1, %g2, %g3 ! get Context |
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112 | bnz 0f ! Context is non-zero |
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113 | andncc %g1, %g2, %g3 ! get page address into %g3 |
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114 | bz 0f ! page address is zero |
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115 | |||
116 | sethi %hi(kernel_8k_tlb_data_template), %g2 |
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117 | ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2 |
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118 | or %g3, %g2, %g2 |
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119 | stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
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120 | retry |
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121 | |||
122 | /* |
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123 | * Third, catch and handle special cases when the trap is caused by |
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124 | * the userspace register window spill or fill handler. In case |
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125 | * one of these two traps caused this trap, we just lower the trap |
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126 | * level and service the DTLB miss. In the end, we restart |
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127 | * the offending SAVE or RESTORE. |
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128 | */ |
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129 | 0: |
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130 | .if (\tl > 0) |
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131 | wrpr %g0, 1, %tl |
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132 | .endif |
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133 | |||
134 | /* |
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135 | * Switch from the MM globals. |
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136 | */ |
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137 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
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138 | |||
139 | /* |
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140 | * Read the Tag Access register for the higher-level handler. |
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141 | * This is necessary to survive nested DTLB misses. |
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142 | */ |
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143 | mov VA_DMMU_TAG_ACCESS, %g2 |
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144 | ldxa [%g2] ASI_DMMU, %g2 |
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145 | |||
146 | /* |
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147 | * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
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148 | */ |
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149 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
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150 | .endm |
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151 | |||
152 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl |
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153 | /* |
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154 | * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
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155 | */ |
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156 | |||
157 | .if (\tl > 0) |
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158 | wrpr %g0, 1, %tl |
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159 | .endif |
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160 | |||
161 | /* |
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162 | * Switch from the MM globals. |
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163 | */ |
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164 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
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165 | |||
166 | /* |
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167 | * Read the Tag Access register for the higher-level handler. |
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168 | * This is necessary to survive nested DTLB misses. |
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169 | */ |
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170 | mov VA_DMMU_TAG_ACCESS, %g2 |
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171 | ldxa [%g2] ASI_DMMU, %g2 |
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172 | |||
173 | /* |
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174 | * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
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175 | */ |
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176 | PREEMPTIBLE_HANDLER fast_data_access_protection |
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177 | .endm |
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178 | |||
179 | #endif /* __ASM__ */ |
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180 | |||
181 | #endif |
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182 | |||
183 | /** @} |
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184 | */ |