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1809 decky 1
/*
2071 jermar 2
 * Copyright (c) 2006 Martin Decky
1809 decky 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1952 jermar 29
/** @addtogroup ia32xen_mm 
1809 decky 30
 * @{
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 */
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/** @file
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 */
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1952 jermar 35
#ifndef KERN_ia32xen_PAGE_H_
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#define KERN_ia32xen_PAGE_H_
1809 decky 37
 
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#include <arch/mm/frame.h>
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#define PAGE_WIDTH  FRAME_WIDTH
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#define PAGE_SIZE   FRAME_SIZE
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#ifdef KERNEL
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#ifndef __ASM__
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#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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#else
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#   define KA2PA(x) ((x) - 0x80000000)
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#   define PA2KA(x) ((x) + 0x80000000)
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#endif
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/*
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 * Implementation of generic 4-level page table interface.
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 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
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 */
2467 jermar 57
 
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/* Number of entries in each level. */
1809 decky 59
#define PTL0_ENTRIES_ARCH   1024
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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#define PTL3_ENTRIES_ARCH   1024
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2467 jermar 64
/* Page table size for each level. */
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#define PTL0_SIZE_ARCH      ONE_FRAME
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#define PTL1_SIZE_ARCH      0
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#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH      ONE_FRAME
2465 jermar 69
 
2467 jermar 70
/* Macros calculating indices into page tables in each level. */
1821 decky 71
#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
1809 decky 72
#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
1821 decky 74
#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
1809 decky 75
 
2467 jermar 76
/* Get PTE address accessors for each level. */
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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    ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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    (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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    (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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    ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
1809 decky 85
 
2467 jermar 86
/* Set PTE address accessors for each level. */
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#define SET_PTL0_ADDRESS_ARCH(ptl0) \
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{ \
1821 decky 89
    mmuext_op_t mmu_ext; \
1824 decky 90
    \
1821 decky 91
    mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
1824 decky 92
    mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
2017 decky 93
    ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
1821 decky 94
}
1824 decky 95
 
2467 jermar 96
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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{ \
2017 decky 98
    mmuext_op_t mmu_ext; \
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    \
100
    mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \
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    mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \
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    ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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    \
1821 decky 104
    mmu_update_t update; \
1824 decky 105
    \
1821 decky 106
    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
2017 decky 107
    update.val = PA2MA(a); \
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    ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
1821 decky 109
}
2017 decky 110
 
1809 decky 111
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
2467 jermar 113
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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{ \
2017 decky 115
    mmu_update_t update; \
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    \
117
    update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \
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    update.val = PA2MA(a); \
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    ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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}
1809 decky 121
 
2467 jermar 122
/* Get PTE flags accessors for each level. */
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#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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    get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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    PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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    PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
130
    get_pt_flags((pte_t *) (ptl3), (index_t) (i))
1809 decky 131
 
2467 jermar 132
/* Set PTE flags accessors for each level. */
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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    set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
1809 decky 135
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
2467 jermar 137
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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    set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
1809 decky 139
 
2467 jermar 140
/* Query macros for the last level. */
141
#define PTE_VALID_ARCH(p) \
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    (*((uint32_t *) (p)) != 0)
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#define PTE_PRESENT_ARCH(p) \
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    ((p)->present != 0)
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#define PTE_GET_FRAME_ARCH(p) \
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    ((p)->frame_address << FRAME_WIDTH)
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#define PTE_WRITABLE_ARCH(p) \
148
    ((p)->writeable != 0)
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#define PTE_EXECUTABLE_ARCH(p) \
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    1
1809 decky 151
 
152
#ifndef __ASM__
153
 
2089 decky 154
#include <mm/mm.h>
1824 decky 155
#include <arch/hypercall.h>
2089 decky 156
#include <arch/interrupt.h>
1809 decky 157
 
158
/* Page fault error codes. */
159
 
2467 jermar 160
/** When bit on this position is 0, the page fault was caused by a not-present
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 * page.
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 */
1821 decky 163
#define PFERR_CODE_P        (1 << 0)
1809 decky 164
 
165
/** When bit on this position is 1, the page fault was caused by a write. */
1821 decky 166
#define PFERR_CODE_RW       (1 << 1)
1809 decky 167
 
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/** When bit on this position is 1, the page fault was caused in user mode. */
1821 decky 169
#define PFERR_CODE_US       (1 << 2)
1809 decky 170
 
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/** When bit on this position is 1, a reserved bit was set in page directory. */
1821 decky 172
#define PFERR_CODE_RSVD     (1 << 3)
1809 decky 173
 
1824 decky 174
typedef struct {
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    uint64_t ptr;      /**< Machine address of PTE */
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    union {            /**< New contents of PTE */
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        uint64_t val;
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        pte_t pte;
179
    };
180
} mmu_update_t;
181
 
182
typedef struct {
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    unsigned int cmd;
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    union {
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        unsigned long mfn;
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        unsigned long linear_addr;
187
    };
188
    union {
189
        unsigned int nr_ents;
190
        void *vcpumask;
191
    };
192
} mmuext_op_t;
193
 
2467 jermar 194
static inline int xen_update_va_mapping(const void *va, const pte_t pte,
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    const unsigned int flags)
1824 decky 196
{
197
    return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
198
}
199
 
2467 jermar 200
static inline int xen_mmu_update(const mmu_update_t *req,
201
    const unsigned int count, unsigned int *success_count, domid_t domid)
1824 decky 202
{
203
    return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
204
}
205
 
2467 jermar 206
static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count,
207
    unsigned int *success_count, domid_t domid)
1824 decky 208
{
209
    return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
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}
211
 
1809 decky 212
static inline int get_pt_flags(pte_t *pt, index_t i)
213
{
214
    pte_t *p = &pt[i];
215
 
2467 jermar 216
    return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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        (!p->present) << PAGE_PRESENT_SHIFT |
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        p->uaccessible << PAGE_USER_SHIFT |
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        1 << PAGE_READ_SHIFT |
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        p->writeable << PAGE_WRITE_SHIFT |
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        1 << PAGE_EXEC_SHIFT |
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        p->global << PAGE_GLOBAL_SHIFT);
1809 decky 223
}
224
 
225
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
226
{
2017 decky 227
    pte_t p = pt[i];
1809 decky 228
 
2017 decky 229
    p.page_cache_disable = !(flags & PAGE_CACHEABLE);
230
    p.present = !(flags & PAGE_NOT_PRESENT);
231
    p.uaccessible = (flags & PAGE_USER) != 0;
232
    p.writeable = (flags & PAGE_WRITE) != 0;
233
    p.global = (flags & PAGE_GLOBAL) != 0;
1809 decky 234
 
235
    /*
236
     * Ensure that there is at least one bit set even if the present bit is cleared.
237
     */
2017 decky 238
    p.soft_valid = true;
239
 
240
    mmu_update_t update;
241
 
242
    update.ptr = PA2MA(KA2PA(&(pt[i])));
243
    update.pte = p;
244
    xen_mmu_update(&update, 1, NULL, DOMID_SELF);
1809 decky 245
}
246
 
247
extern void page_arch_init(void);
248
extern void page_fault(int n, istate_t *istate);
249
 
250
#endif /* __ASM__ */
251
 
252
#endif /* KERNEL */
253
 
254
#endif
255
 
256
/** @}
257
 */