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2464 jermar 1 
/*
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 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup arm32mm
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 * @{
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 */
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/** @file
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 *  @brief Page fault related functions.
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 */
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#include <panic.h>
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#include <arch/exception.h>
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#include <arch/debug/print.h>
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#include <arch/mm/page_fault.h>
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#include <mm/as.h>
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#include <genarch/mm/page_pt.h>
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#include <arch.h>
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#include <interrupt.h>
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#include <print.h>
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/** Returns value stored in fault status register.
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 *
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 *  @return Value stored in CP15 fault status register (FSR).
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 */
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static inline fault_status_t read_fault_status_register(void)
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{
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    fault_status_union_t fsu;
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    /* fault status is stored in CP15 register 5 */
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    asm volatile (
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        "mrc p15, 0, %[dummy], c5, c0, 0"
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        : [dummy] "=r" (fsu.dummy)
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    );
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    return fsu.fs;
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}
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/** Returns FAR (fault address register) content.
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 *
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 * @return FAR (fault address register) content (address that caused a page
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 *         fault)
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 */
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static inline uintptr_t read_fault_address_register(void)
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{
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    uintptr_t ret;
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    /* fault adress is stored in CP15 register 6 */
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    asm volatile (
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        "mrc p15, 0, %[ret], c6, c0, 0"
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        : [ret] "=r" (ret)
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    );
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    return ret;
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}
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/** Decides whether the instruction is load/store or not.
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 *
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 * @param instr Instruction
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 *
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 * @return true when instruction is load/store, false otherwise
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 *
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 */
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static inline bool is_load_store_instruction(instruction_t instr)
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{
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    /* load store immediate offset */
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    if (instr.type == 0x2)
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        return true;
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    /* load store register offset */
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    if ((instr.type == 0x3) && (instr.bit4 == 0))
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        return true;
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    /* load store multiple */
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    if (instr.type == 0x4)
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        return true;
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    /* oprocessor load/store */
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    if (instr.type == 0x6)
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        return true;
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    return false;
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}
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/** Decides whether the instruction is swap or not.
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 *
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 * @param instr Instruction
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 *
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 * @return true when instruction is swap, false otherwise
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 */
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static inline bool is_swap_instruction(instruction_t instr)
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{
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    /* swap, swapb instruction */
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    if ((instr.type == 0x0) &&
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        ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
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        (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
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        return true;
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    return false;
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}
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/** Decides whether read or write into memory is requested.
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 *
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 * @param instr_addr   Address of instruction which tries to access memory.
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 * @param badvaddr     Virtual address the instruction tries to access.
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 *
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 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
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 *     requested.
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 */
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static pf_access_t get_memory_access_type(uint32_t instr_addr,
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    uintptr_t badvaddr)
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{
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    instruction_union_t instr_union;
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    instr_union.pc = instr_addr;
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    instruction_t instr = *(instr_union.instr);
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    /* undefined instructions */
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    if (instr.condition == 0xf) {
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        panic("page_fault - instruction does not access memory "
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            "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
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        return PF_ACCESS_EXEC;
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    }
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    /* load store instructions */
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    if (is_load_store_instruction(instr)) {
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        if (instr.access == 1) {
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            return PF_ACCESS_READ;
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        } else {
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            return PF_ACCESS_WRITE;
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        }
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    }
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    /* swap, swpb instruction */
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    if (is_swap_instruction(instr)) {
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        return PF_ACCESS_WRITE;
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    }
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    panic("page_fault - instruction doesn't access memory "
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        "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
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    return PF_ACCESS_EXEC;
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}
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/** Handles "data abort" exception (load or store at invalid address).
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 *
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 * @param exc_no    Exception number.
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 * @param istate    CPU state when exception occured.
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 */
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void data_abort(int exc_no, istate_t *istate)
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{
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    fault_status_t fsr __attribute__ ((unused)) =
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        read_fault_status_register();
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    uintptr_t badvaddr = read_fault_address_register();
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    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
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    int ret = as_page_fault(badvaddr, access, istate);
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    if (ret == AS_PF_FAULT) {
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        print_istate(istate);
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        dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
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            "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
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            access);
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        fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
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        panic("Page fault.");
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    }
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}
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/** Handles "prefetch abort" exception (instruction couldn't be executed).
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 *
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 * @param exc_no    Exception number.
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 * @param istate    CPU state when exception occured.
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 */
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void prefetch_abort(int exc_no, istate_t *istate)
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{
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    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
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    if (ret == AS_PF_FAULT) {
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        dprintf("prefetch_abort\n");
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        print_istate(istate);
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        panic("page fault - prefetch_abort at address: %x.",
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            istate->pc);
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    }
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}
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/** @}
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 */