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| Rev | Author | Line No. | Line |
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| 4300 | trochtova | 1 | /* |
| 2 | * The PCI Library -- Direct Configuration access via i386 Ports |
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| 3 | * |
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| 4 | * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz> |
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| 5 | * |
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| 6 | * May 8, 2006 - Modified and ported to HelenOS by Jakub Jermar. |
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| 7 | * |
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| 8 | * Can be freely distributed and used under the terms of the GNU GPL. |
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| 9 | */ |
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| 10 | |||
| 11 | #include <unistd.h> |
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| 12 | #include <ddi.h> |
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| 13 | #include <libarch/ddi.h> |
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| 14 | |||
| 15 | #include "internal.h" |
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| 16 | |||
| 17 | #define PCI_CONF1 0xcf8 |
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| 18 | #define PCI_CONF1_SIZE 8 |
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| 19 | |||
| 20 | |||
| 21 | static void conf12_init(struct pci_access *a) |
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| 22 | { |
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| 23 | } |
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| 24 | |||
| 25 | static void conf12_cleanup(struct pci_access *a UNUSED) |
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| 26 | { |
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| 27 | } |
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| 28 | |||
| 29 | /* |
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| 30 | * Before we decide to use direct hardware access mechanisms, we try to do some |
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| 31 | * trivial checks to ensure it at least _seems_ to be working -- we just test |
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| 32 | * whether bus 00 contains a host bridge (this is similar to checking |
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| 33 | * techniques used in XFree86, but ours should be more reliable since we |
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| 34 | * attempt to make use of direct access hints provided by the PCI BIOS). |
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| 35 | * |
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| 36 | * This should be close to trivial, but it isn't, because there are buggy |
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| 37 | * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. |
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| 38 | */ |
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| 39 | |||
| 40 | static int intel_sanity_check(struct pci_access *a, struct pci_methods *m) |
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| 41 | { |
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| 42 | struct pci_dev d; |
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| 43 | |||
| 44 | a->debug("...sanity check"); |
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| 45 | d.bus = 0; |
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| 46 | d.func = 0; |
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| 47 | for (d.dev = 0; d.dev < 32; d.dev++) { |
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| 48 | u16 class, vendor; |
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| 49 | if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class, |
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| 50 | sizeof(class)) |
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| 51 | && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) |
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| 52 | || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) |
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| 53 | || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor, |
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| 54 | sizeof(vendor)) |
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| 55 | && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) |
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| 56 | || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) { |
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| 57 | a->debug("...outside the Asylum at 0/%02x/0", |
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| 58 | d.dev); |
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| 59 | return 1; |
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| 60 | } |
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| 61 | } |
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| 62 | a->debug("...insane"); |
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| 63 | return 0; |
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| 64 | } |
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| 65 | |||
| 66 | /* |
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| 67 | * Configuration type 1 |
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| 68 | */ |
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| 69 | |||
| 70 | #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3)) |
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| 71 | |||
| 72 | static int conf1_detect(struct pci_access *a) |
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| 73 | { |
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| 74 | unsigned int tmp; |
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| 75 | int res = 0; |
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| 76 | |||
| 77 | /* |
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| 78 | * Gain control over PCI configuration ports. |
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| 79 | */ |
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| 80 | void * addr; |
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| 81 | if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) { |
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| 82 | return 0; |
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| 83 | } |
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| 84 | |||
| 85 | pio_write_8(0xCFB, 0x01); |
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| 86 | tmp = pio_read_32(0xCF8); |
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| 87 | pio_write_32(0xCF8, 0x80000000); |
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| 88 | if (pio_read_32(0xCF8) == 0x80000000) { |
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| 89 | res = 1; |
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| 90 | } |
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| 91 | pio_write_32(0xCF8, tmp); |
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| 92 | if (res) { |
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| 93 | res = intel_sanity_check(a, &pm_intel_conf1); |
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| 94 | } |
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| 95 | return res; |
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| 96 | } |
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| 97 | |||
| 98 | static int conf1_read(struct pci_dev *d, int pos, byte * buf, int len) |
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| 99 | { |
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| 100 | int addr = 0xcfc + (pos & 3); |
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| 101 | |||
| 102 | if (pos >= 256) |
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| 103 | return 0; |
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| 104 | |||
| 105 | pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) | |
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| 106 | (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3)); |
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| 107 | |||
| 108 | switch (len) { |
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| 109 | case 1: |
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| 110 | buf[0] = pio_read_8(addr); |
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| 111 | break; |
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| 112 | case 2: |
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| 113 | ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); |
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| 114 | break; |
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| 115 | case 4: |
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| 116 | ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); |
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| 117 | break; |
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| 118 | default: |
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| 119 | return pci_generic_block_read(d, pos, buf, len); |
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| 120 | } |
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| 121 | return 1; |
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| 122 | } |
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| 123 | |||
| 124 | static int conf1_write(struct pci_dev *d, int pos, byte * buf, int len) |
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| 125 | { |
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| 126 | int addr = 0xcfc + (pos & 3); |
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| 127 | |||
| 128 | if (pos >= 256) |
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| 129 | return 0; |
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| 130 | |||
| 131 | pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) | |
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| 132 | (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3)); |
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| 133 | |||
| 134 | switch (len) { |
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| 135 | case 1: |
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| 136 | pio_write_8(addr, buf[0]); |
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| 137 | break; |
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| 138 | case 2: |
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| 139 | pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0])); |
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| 140 | break; |
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| 141 | case 4: |
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| 142 | pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0])); |
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| 143 | break; |
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| 144 | default: |
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| 145 | return pci_generic_block_write(d, pos, buf, len); |
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| 146 | } |
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| 147 | return 1; |
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| 148 | } |
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| 149 | |||
| 150 | /* |
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| 151 | * Configuration type 2. Obsolete and brain-damaged, but existing. |
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| 152 | */ |
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| 153 | |||
| 154 | static int conf2_detect(struct pci_access *a) |
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| 155 | { |
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| 156 | /* |
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| 157 | * Gain control over PCI configuration ports. |
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| 158 | */ |
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| 159 | void * addr; |
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| 160 | if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) { |
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| 161 | return 0; |
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| 162 | } |
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| 163 | if (pio_enable((void *)0xC000, 0x1000, &addr)) { |
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| 164 | return 0; |
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| 165 | } |
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| 166 | |||
| 167 | /* This is ugly and tends to produce false positives. Beware. */ |
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| 168 | pio_write_8(0xCFB, 0x00); |
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| 169 | pio_write_8(0xCF8, 0x00); |
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| 170 | pio_write_8(0xCFA, 0x00); |
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| 171 | if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00) |
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| 172 | return intel_sanity_check(a, &pm_intel_conf2); |
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| 173 | else |
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| 174 | return 0; |
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| 175 | } |
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| 176 | |||
| 177 | static int conf2_read(struct pci_dev *d, int pos, byte * buf, int len) |
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| 178 | { |
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| 179 | int addr = 0xc000 | (d->dev << 8) | pos; |
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| 180 | |||
| 181 | if (pos >= 256) |
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| 182 | return 0; |
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| 183 | |||
| 184 | if (d->dev >= 16) |
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| 185 | /* conf2 supports only 16 devices per bus */ |
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| 186 | return 0; |
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| 187 | pio_write_8(0xcf8, (d->func << 1) | 0xf0); |
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| 188 | pio_write_8(0xcfa, d->bus); |
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| 189 | switch (len) { |
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| 190 | case 1: |
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| 191 | buf[0] = pio_read_8(addr); |
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| 192 | break; |
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| 193 | case 2: |
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| 194 | ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); |
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| 195 | break; |
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| 196 | case 4: |
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| 197 | ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); |
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| 198 | break; |
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| 199 | default: |
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| 200 | pio_write_8(0xcf8, 0); |
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| 201 | return pci_generic_block_read(d, pos, buf, len); |
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| 202 | } |
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| 203 | pio_write_8(0xcf8, 0); |
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| 204 | return 1; |
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| 205 | } |
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| 206 | |||
| 207 | static int conf2_write(struct pci_dev *d, int pos, byte * buf, int len) |
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| 208 | { |
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| 209 | int addr = 0xc000 | (d->dev << 8) | pos; |
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| 210 | |||
| 211 | if (pos >= 256) |
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| 212 | return 0; |
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| 213 | |||
| 214 | if (d->dev >= 16) |
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| 215 | d->access->error("conf2_write: only first 16 devices exist."); |
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| 216 | pio_write_8(0xcf8, (d->func << 1) | 0xf0); |
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| 217 | pio_write_8(0xcfa, d->bus); |
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| 218 | switch (len) { |
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| 219 | case 1: |
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| 220 | pio_write_8(addr, buf[0]); |
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| 221 | break; |
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| 222 | case 2: |
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| 223 | pio_write_16(addr, le16_to_cpu(*(u16 *) buf)); |
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| 224 | break; |
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| 225 | case 4: |
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| 226 | pio_write_32(addr, le32_to_cpu(*(u32 *) buf)); |
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| 227 | break; |
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| 228 | default: |
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| 229 | pio_write_8(0xcf8, 0); |
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| 230 | return pci_generic_block_write(d, pos, buf, len); |
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| 231 | } |
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| 232 | pio_write_8(0xcf8, 0); |
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| 233 | return 1; |
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| 234 | } |
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| 235 | |||
| 236 | struct pci_methods pm_intel_conf1 = { |
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| 237 | "Intel-conf1", |
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| 238 | NULL, /* config */ |
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| 239 | conf1_detect, |
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| 240 | conf12_init, |
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| 241 | conf12_cleanup, |
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| 242 | pci_generic_scan, |
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| 243 | pci_generic_fill_info, |
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| 244 | conf1_read, |
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| 245 | conf1_write, |
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| 246 | NULL, /* init_dev */ |
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| 247 | NULL /* cleanup_dev */ |
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| 248 | }; |
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| 249 | |||
| 250 | struct pci_methods pm_intel_conf2 = { |
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| 251 | "Intel-conf2", |
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| 252 | NULL, /* config */ |
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| 253 | conf2_detect, |
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| 254 | conf12_init, |
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| 255 | conf12_cleanup, |
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| 256 | pci_generic_scan, |
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| 257 | pci_generic_fill_info, |
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| 258 | conf2_read, |
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| 259 | conf2_write, |
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| 260 | NULL, /* init_dev */ |
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| 261 | NULL /* cleanup_dev */ |
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| 262 | }; |