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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4300 | trochtova | 1 | /* |
| 2 | * The PCI Library -- PCI Header Structure (based on <linux/pci.h>) |
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| 3 | * |
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| 4 | * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz> |
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| 5 | * |
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| 6 | * May 8, 2006 - Modified and ported to HelenOS by Jakub Jermar. |
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| 7 | * |
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| 8 | * Can be freely distributed and used under the terms of the GNU GPL. |
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| 9 | */ |
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| 10 | |||
| 11 | /* |
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| 12 | * Under PCI, each device has 256 bytes of configuration address space, |
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| 13 | * of which the first 64 bytes are standardized as follows: |
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| 14 | */ |
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| 15 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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| 16 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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| 17 | #define PCI_COMMAND 0x04 /* 16 bits */ |
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| 18 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
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| 19 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
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| 20 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ |
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| 21 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ |
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| 22 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
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| 23 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
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| 24 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
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| 25 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
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| 26 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
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| 27 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
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| 28 | |||
| 29 | #define PCI_STATUS 0x06 /* 16 bits */ |
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| 30 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
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| 31 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
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| 32 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
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| 33 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
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| 34 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
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| 35 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
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| 36 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
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| 37 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
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| 38 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
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| 39 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
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| 40 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
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| 41 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
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| 42 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
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| 43 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
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| 44 | |||
| 45 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
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| 46 | revision */ |
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| 47 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
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| 48 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
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| 49 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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| 50 | |||
| 51 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
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| 52 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
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| 53 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
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| 54 | #define PCI_HEADER_TYPE_NORMAL 0 |
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| 55 | #define PCI_HEADER_TYPE_BRIDGE 1 |
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| 56 | #define PCI_HEADER_TYPE_CARDBUS 2 |
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| 57 | |||
| 58 | #define PCI_BIST 0x0f /* 8 bits */ |
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| 59 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
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| 60 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
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| 61 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
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| 62 | |||
| 63 | /* |
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| 64 | * Base addresses specify locations in memory or I/O space. |
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| 65 | * Decoded size can be determined by writing a value of |
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| 66 | * 0xffffffff to the register, and reading it back. Only |
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| 67 | * 1 bits are decoded. |
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| 68 | */ |
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| 69 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
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| 70 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
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| 71 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
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| 72 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
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| 73 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
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| 74 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
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| 75 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
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| 76 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
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| 77 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
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| 78 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
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| 79 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
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| 80 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
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| 81 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
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| 82 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
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| 83 | #define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f) |
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| 84 | #define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03) |
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| 85 | /* bit 1 is reserved if address_space = 1 */ |
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| 86 | |||
| 87 | /* Header type 0 (normal devices) */ |
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| 88 | #define PCI_CARDBUS_CIS 0x28 |
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| 89 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
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| 90 | #define PCI_SUBSYSTEM_ID 0x2e |
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| 91 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
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| 92 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
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| 93 | #define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff) |
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| 94 | |||
| 95 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
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| 96 | |||
| 97 | /* 0x35-0x3b are reserved */ |
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| 98 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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| 99 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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| 100 | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
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| 101 | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
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| 102 | |||
| 103 | /* Header type 1 (PCI-to-PCI bridges) */ |
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| 104 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
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| 105 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
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| 106 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
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| 107 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ |
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| 108 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
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| 109 | #define PCI_IO_LIMIT 0x1d |
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| 110 | #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ |
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| 111 | #define PCI_IO_RANGE_TYPE_16 0x00 |
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| 112 | #define PCI_IO_RANGE_TYPE_32 0x01 |
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| 113 | #define PCI_IO_RANGE_MASK ~0x0f |
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| 114 | #define PCI_SEC_STATUS 0x1e /* Secondary status register */ |
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| 115 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
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| 116 | #define PCI_MEMORY_LIMIT 0x22 |
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| 117 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f |
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| 118 | #define PCI_MEMORY_RANGE_MASK ~0x0f |
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| 119 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ |
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| 120 | #define PCI_PREF_MEMORY_LIMIT 0x26 |
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| 121 | #define PCI_PREF_RANGE_TYPE_MASK 0x0f |
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| 122 | #define PCI_PREF_RANGE_TYPE_32 0x00 |
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| 123 | #define PCI_PREF_RANGE_TYPE_64 0x01 |
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| 124 | #define PCI_PREF_RANGE_MASK ~0x0f |
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| 125 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
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| 126 | #define PCI_PREF_LIMIT_UPPER32 0x2c |
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| 127 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
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| 128 | #define PCI_IO_LIMIT_UPPER16 0x32 |
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| 129 | /* 0x34 same as for htype 0 */ |
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| 130 | /* 0x35-0x3b is reserved */ |
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| 131 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
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| 132 | /* 0x3c-0x3d are same as for htype 0 */ |
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| 133 | #define PCI_BRIDGE_CONTROL 0x3e |
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| 134 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
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| 135 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
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| 136 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
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| 137 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
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| 138 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
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| 139 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
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| 140 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
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| 141 | |||
| 142 | /* Header type 2 (CardBus bridges) */ |
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| 143 | /* 0x14-0x15 reserved */ |
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| 144 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ |
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| 145 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ |
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| 146 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ |
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| 147 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ |
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| 148 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ |
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| 149 | #define PCI_CB_MEMORY_BASE_0 0x1c |
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| 150 | #define PCI_CB_MEMORY_LIMIT_0 0x20 |
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| 151 | #define PCI_CB_MEMORY_BASE_1 0x24 |
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| 152 | #define PCI_CB_MEMORY_LIMIT_1 0x28 |
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| 153 | #define PCI_CB_IO_BASE_0 0x2c |
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| 154 | #define PCI_CB_IO_BASE_0_HI 0x2e |
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| 155 | #define PCI_CB_IO_LIMIT_0 0x30 |
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| 156 | #define PCI_CB_IO_LIMIT_0_HI 0x32 |
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| 157 | #define PCI_CB_IO_BASE_1 0x34 |
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| 158 | #define PCI_CB_IO_BASE_1_HI 0x36 |
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| 159 | #define PCI_CB_IO_LIMIT_1 0x38 |
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| 160 | #define PCI_CB_IO_LIMIT_1_HI 0x3a |
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| 161 | #define PCI_CB_IO_RANGE_MASK ~0x03 |
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| 162 | /* 0x3c-0x3d are same as for htype 0 */ |
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| 163 | #define PCI_CB_BRIDGE_CONTROL 0x3e |
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| 164 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ |
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| 165 | #define PCI_CB_BRIDGE_CTL_SERR 0x02 |
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| 166 | #define PCI_CB_BRIDGE_CTL_ISA 0x04 |
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| 167 | #define PCI_CB_BRIDGE_CTL_VGA 0x08 |
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| 168 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 |
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| 169 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ |
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| 170 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ |
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| 171 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ |
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| 172 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 |
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| 173 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 |
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| 174 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
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| 175 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
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| 176 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ |
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| 177 | /* 0x48-0x7f reserved */ |
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| 178 | |||
| 179 | /* Capability lists */ |
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| 180 | |||
| 181 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
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| 182 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
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| 183 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
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| 184 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
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| 185 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
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| 186 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
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| 187 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
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| 188 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
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| 189 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
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| 190 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ |
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| 191 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
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| 192 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ |
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| 193 | #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ |
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| 194 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
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| 195 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
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| 196 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
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| 197 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
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| 198 | #define PCI_CAP_SIZEOF 4 |
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| 199 | |||
| 200 | /* Capabilities residing in the PCI Express extended configuration space */ |
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| 201 | |||
| 202 | #define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */ |
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| 203 | #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */ |
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| 204 | #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ |
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| 205 | #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ |
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| 206 | |||
| 207 | /* Power Management Registers */ |
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| 208 | |||
| 209 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ |
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| 210 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ |
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| 211 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */ |
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| 212 | #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */ |
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| 213 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
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| 214 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
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| 215 | #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ |
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| 216 | #define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */ |
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| 217 | #define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */ |
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| 218 | #define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */ |
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| 219 | #define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */ |
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| 220 | #define PCI_PM_CTRL 4 /* PM control and status register */ |
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| 221 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
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| 222 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
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| 223 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */ |
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| 224 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */ |
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| 225 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ |
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| 226 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */ |
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| 227 | #define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */ |
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| 228 | #define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */ |
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| 229 | #define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */ |
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| 230 | #define PCI_PM_SIZEOF 8 |
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| 231 | |||
| 232 | /* AGP registers */ |
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| 233 | |||
| 234 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
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| 235 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
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| 236 | #define PCI_AGP_STATUS 4 /* Status register */ |
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| 237 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
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| 238 | #define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */ |
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| 239 | #define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ |
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| 240 | #define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */ |
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| 241 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
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| 242 | #define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */ |
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| 243 | #define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */ |
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| 244 | #define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */ |
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| 245 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */ |
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| 246 | #define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */ |
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| 247 | #define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */ |
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| 248 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */ |
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| 249 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */ |
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| 250 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ |
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| 251 | #define PCI_AGP_COMMAND 8 /* Control register */ |
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| 252 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
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| 253 | #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ |
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| 254 | #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ |
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| 255 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
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| 256 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
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| 257 | #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ |
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| 258 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ |
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| 259 | #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ |
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| 260 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ |
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| 261 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ |
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| 262 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ |
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| 263 | #define PCI_AGP_SIZEOF 12 |
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| 264 | |||
| 265 | /* Slot Identification */ |
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| 266 | |||
| 267 | #define PCI_SID_ESR 2 /* Expansion Slot Register */ |
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| 268 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ |
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| 269 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ |
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| 270 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ |
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| 271 | |||
| 272 | /* Message Signalled Interrupts registers */ |
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| 273 | |||
| 274 | #define PCI_MSI_FLAGS 2 /* Various flags */ |
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| 275 | #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ |
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| 276 | #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ |
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| 277 | #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ |
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| 278 | #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ |
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| 279 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
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| 280 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ |
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| 281 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
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| 282 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
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| 283 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
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| 284 | |||
| 285 | /* PCI-X */ |
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| 286 | #define PCI_PCIX_COMMAND 2 /* Command register offset */ |
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| 287 | #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ |
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| 288 | #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ |
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| 289 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ |
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| 290 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 |
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| 291 | #define PCI_PCIX_COMMAND_RESERVED 0xf80 |
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| 292 | #define PCI_PCIX_STATUS 4 /* Status register offset */ |
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| 293 | #define PCI_PCIX_STATUS_FUNCTION 0x00000007 |
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| 294 | #define PCI_PCIX_STATUS_DEVICE 0x000000f8 |
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| 295 | #define PCI_PCIX_STATUS_BUS 0x0000ff00 |
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| 296 | #define PCI_PCIX_STATUS_64BIT 0x00010000 |
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| 297 | #define PCI_PCIX_STATUS_133MHZ 0x00020000 |
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| 298 | #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ |
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| 299 | #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ |
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| 300 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ |
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| 301 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ |
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| 302 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 |
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| 303 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 |
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| 304 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ |
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| 305 | #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
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| 306 | #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
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| 307 | #define PCI_PCIX_SIZEOF 4 |
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| 308 | |||
| 309 | /* PCI-X Bridges */ |
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| 310 | #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ |
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| 311 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 |
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| 312 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 |
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| 313 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ |
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| 314 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ |
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| 315 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ |
||
| 316 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 |
||
| 317 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 |
||
| 318 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 |
||
| 319 | #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ |
||
| 320 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 |
||
| 321 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 |
||
| 322 | #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 |
||
| 323 | #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 |
||
| 324 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 |
||
| 325 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ |
||
| 326 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ |
||
| 327 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ |
||
| 328 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 |
||
| 329 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 |
||
| 330 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ |
||
| 331 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ |
||
| 332 | #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff |
||
| 333 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 |
||
| 334 | #define PCI_PCIX_BRIDGE_SIZEOF 12 |
||
| 335 | |||
| 336 | /* HyperTransport (as of spec rev. 2.00) */ |
||
| 337 | #define PCI_HT_CMD 2 /* Command Register */ |
||
| 338 | #define PCI_HT_CMD_TYP_HI 0xe000 /* Capability Type high part */ |
||
| 339 | #define PCI_HT_CMD_TYP_HI_PRI 0x0000 /* Slave or Primary Interface */ |
||
| 340 | #define PCI_HT_CMD_TYP_HI_SEC 0x2000 /* Host or Secondary Interface */ |
||
| 341 | #define PCI_HT_CMD_TYP 0xf800 /* Capability Type */ |
||
| 342 | #define PCI_HT_CMD_TYP_SW 0x4000 /* Switch */ |
||
| 343 | #define PCI_HT_CMD_TYP_IDC 0x8000 /* Interrupt Discovery and Configuration */ |
||
| 344 | #define PCI_HT_CMD_TYP_RID 0x8800 /* Revision ID */ |
||
| 345 | #define PCI_HT_CMD_TYP_UIDC 0x9000 /* UnitID Clumping */ |
||
| 346 | #define PCI_HT_CMD_TYP_ECSA 0x9800 /* Extended Configuration Space Access */ |
||
| 347 | #define PCI_HT_CMD_TYP_AM 0xa000 /* Address Mapping */ |
||
| 348 | #define PCI_HT_CMD_TYP_MSIM 0xa800 /* MSI Mapping */ |
||
| 349 | #define PCI_HT_CMD_TYP_DR 0xb000 /* DirectRoute */ |
||
| 350 | #define PCI_HT_CMD_TYP_VCS 0xb800 /* VCSet */ |
||
| 351 | #define PCI_HT_CMD_TYP_RM 0xc000 /* Retry Mode */ |
||
| 352 | #define PCI_HT_CMD_TYP_X86 0xc800 /* X86 (reserved) */ |
||
| 353 | |||
| 354 | /* Link Control Register */ |
||
| 355 | #define PCI_HT_LCTR_CFLE 0x0002 /* CRC Flood Enable */ |
||
| 356 | #define PCI_HT_LCTR_CST 0x0004 /* CRC Start Test */ |
||
| 357 | #define PCI_HT_LCTR_CFE 0x0008 /* CRC Force Error */ |
||
| 358 | #define PCI_HT_LCTR_LKFAIL 0x0010 /* Link Failure */ |
||
| 359 | #define PCI_HT_LCTR_INIT 0x0020 /* Initialization Complete */ |
||
| 360 | #define PCI_HT_LCTR_EOC 0x0040 /* End of Chain */ |
||
| 361 | #define PCI_HT_LCTR_TXO 0x0080 /* Transmitter Off */ |
||
| 362 | #define PCI_HT_LCTR_CRCERR 0x0f00 /* CRC Error */ |
||
| 363 | #define PCI_HT_LCTR_ISOCEN 0x1000 /* Isochronous Flow Control Enable */ |
||
| 364 | #define PCI_HT_LCTR_LSEN 0x2000 /* LDTSTOP# Tristate Enable */ |
||
| 365 | #define PCI_HT_LCTR_EXTCTL 0x4000 /* Extended CTL Time */ |
||
| 366 | #define PCI_HT_LCTR_64B 0x8000 /* 64-bit Addressing Enable */ |
||
| 367 | |||
| 368 | /* Link Configuration Register */ |
||
| 369 | #define PCI_HT_LCNF_MLWI 0x0007 /* Max Link Width In */ |
||
| 370 | #define PCI_HT_LCNF_LW_8B 0x0 /* Link Width 8 bits */ |
||
| 371 | #define PCI_HT_LCNF_LW_16B 0x1 /* Link Width 16 bits */ |
||
| 372 | #define PCI_HT_LCNF_LW_32B 0x3 /* Link Width 32 bits */ |
||
| 373 | #define PCI_HT_LCNF_LW_2B 0x4 /* Link Width 2 bits */ |
||
| 374 | #define PCI_HT_LCNF_LW_4B 0x5 /* Link Width 4 bits */ |
||
| 375 | #define PCI_HT_LCNF_LW_NC 0x7 /* Link physically not connected */ |
||
| 376 | #define PCI_HT_LCNF_DFI 0x0008 /* Doubleword Flow Control In */ |
||
| 377 | #define PCI_HT_LCNF_MLWO 0x0070 /* Max Link Width Out */ |
||
| 378 | #define PCI_HT_LCNF_DFO 0x0080 /* Doubleword Flow Control Out */ |
||
| 379 | #define PCI_HT_LCNF_LWI 0x0700 /* Link Width In */ |
||
| 380 | #define PCI_HT_LCNF_DFIE 0x0800 /* Doubleword Flow Control In Enable */ |
||
| 381 | #define PCI_HT_LCNF_LWO 0x7000 /* Link Width Out */ |
||
| 382 | #define PCI_HT_LCNF_DFOE 0x8000 /* Doubleword Flow Control Out Enable */ |
||
| 383 | |||
| 384 | /* Revision ID Register */ |
||
| 385 | #define PCI_HT_RID_MIN 0x1f /* Minor Revision */ |
||
| 386 | #define PCI_HT_RID_MAJ 0xe0 /* Major Revision */ |
||
| 387 | |||
| 388 | /* Link Frequency/Error Register */ |
||
| 389 | #define PCI_HT_LFRER_FREQ 0x0f /* Transmitter Clock Frequency */ |
||
| 390 | #define PCI_HT_LFRER_200 0x00 /* 200MHz */ |
||
| 391 | #define PCI_HT_LFRER_300 0x01 /* 300MHz */ |
||
| 392 | #define PCI_HT_LFRER_400 0x02 /* 400MHz */ |
||
| 393 | #define PCI_HT_LFRER_500 0x03 /* 500MHz */ |
||
| 394 | #define PCI_HT_LFRER_600 0x04 /* 600MHz */ |
||
| 395 | #define PCI_HT_LFRER_800 0x05 /* 800MHz */ |
||
| 396 | #define PCI_HT_LFRER_1000 0x06 /* 1.0GHz */ |
||
| 397 | #define PCI_HT_LFRER_1200 0x07 /* 1.2GHz */ |
||
| 398 | #define PCI_HT_LFRER_1400 0x08 /* 1.4GHz */ |
||
| 399 | #define PCI_HT_LFRER_1600 0x09 /* 1.6GHz */ |
||
| 400 | #define PCI_HT_LFRER_VEND 0x0f /* Vendor-Specific */ |
||
| 401 | #define PCI_HT_LFRER_ERR 0xf0 /* Link Error */ |
||
| 402 | #define PCI_HT_LFRER_PROT 0x10 /* Protocol Error */ |
||
| 403 | #define PCI_HT_LFRER_OV 0x20 /* Overflow Error */ |
||
| 404 | #define PCI_HT_LFRER_EOC 0x40 /* End of Chain Error */ |
||
| 405 | #define PCI_HT_LFRER_CTLT 0x80 /* CTL Timeout */ |
||
| 406 | |||
| 407 | /* Link Frequency Capability Register */ |
||
| 408 | #define PCI_HT_LFCAP_200 0x0001 /* 200MHz */ |
||
| 409 | #define PCI_HT_LFCAP_300 0x0002 /* 300MHz */ |
||
| 410 | #define PCI_HT_LFCAP_400 0x0004 /* 400MHz */ |
||
| 411 | #define PCI_HT_LFCAP_500 0x0008 /* 500MHz */ |
||
| 412 | #define PCI_HT_LFCAP_600 0x0010 /* 600MHz */ |
||
| 413 | #define PCI_HT_LFCAP_800 0x0020 /* 800MHz */ |
||
| 414 | #define PCI_HT_LFCAP_1000 0x0040 /* 1.0GHz */ |
||
| 415 | #define PCI_HT_LFCAP_1200 0x0080 /* 1.2GHz */ |
||
| 416 | #define PCI_HT_LFCAP_1400 0x0100 /* 1.4GHz */ |
||
| 417 | #define PCI_HT_LFCAP_1600 0x0200 /* 1.6GHz */ |
||
| 418 | #define PCI_HT_LFCAP_VEND 0x8000 /* Vendor-Specific */ |
||
| 419 | |||
| 420 | /* Feature Register */ |
||
| 421 | #define PCI_HT_FTR_ISOCFC 0x0001 /* Isochronous Flow Control Mode */ |
||
| 422 | #define PCI_HT_FTR_LDTSTOP 0x0002 /* LDTSTOP# Supported */ |
||
| 423 | #define PCI_HT_FTR_CRCTM 0x0004 /* CRC Test Mode */ |
||
| 424 | #define PCI_HT_FTR_ECTLT 0x0008 /* Extended CTL Time Required */ |
||
| 425 | #define PCI_HT_FTR_64BA 0x0010 /* 64-bit Addressing */ |
||
| 426 | #define PCI_HT_FTR_UIDRD 0x0020 /* UnitID Reorder Disable */ |
||
| 427 | |||
| 428 | /* Error Handling Register */ |
||
| 429 | #define PCI_HT_EH_PFLE 0x0001 /* Protocol Error Flood Enable */ |
||
| 430 | #define PCI_HT_EH_OFLE 0x0002 /* Overflow Error Flood Enable */ |
||
| 431 | #define PCI_HT_EH_PFE 0x0004 /* Protocol Error Fatal Enable */ |
||
| 432 | #define PCI_HT_EH_OFE 0x0008 /* Overflow Error Fatal Enable */ |
||
| 433 | #define PCI_HT_EH_EOCFE 0x0010 /* End of Chain Error Fatal Enable */ |
||
| 434 | #define PCI_HT_EH_RFE 0x0020 /* Response Error Fatal Enable */ |
||
| 435 | #define PCI_HT_EH_CRCFE 0x0040 /* CRC Error Fatal Enable */ |
||
| 436 | #define PCI_HT_EH_SERRFE 0x0080 /* System Error Fatal Enable (B */ |
||
| 437 | #define PCI_HT_EH_CF 0x0100 /* Chain Fail */ |
||
| 438 | #define PCI_HT_EH_RE 0x0200 /* Response Error */ |
||
| 439 | #define PCI_HT_EH_PNFE 0x0400 /* Protocol Error Nonfatal Enable */ |
||
| 440 | #define PCI_HT_EH_ONFE 0x0800 /* Overflow Error Nonfatal Enable */ |
||
| 441 | #define PCI_HT_EH_EOCNFE 0x1000 /* End of Chain Error Nonfatal Enable */ |
||
| 442 | #define PCI_HT_EH_RNFE 0x2000 /* Response Error Nonfatal Enable */ |
||
| 443 | #define PCI_HT_EH_CRCNFE 0x4000 /* CRC Error Nonfatal Enable */ |
||
| 444 | #define PCI_HT_EH_SERRNFE 0x8000 /* System Error Nonfatal Enable */ |
||
| 445 | |||
| 446 | /* HyperTransport: Slave or Primary Interface */ |
||
| 447 | #define PCI_HT_PRI_CMD 2 /* Command Register */ |
||
| 448 | #define PCI_HT_PRI_CMD_BUID 0x001f /* Base UnitID */ |
||
| 449 | #define PCI_HT_PRI_CMD_UC 0x03e0 /* Unit Count */ |
||
| 450 | #define PCI_HT_PRI_CMD_MH 0x0400 /* Master Host */ |
||
| 451 | #define PCI_HT_PRI_CMD_DD 0x0800 /* Default Direction */ |
||
| 452 | #define PCI_HT_PRI_CMD_DUL 0x1000 /* Drop on Uninitialized Link */ |
||
| 453 | |||
| 454 | #define PCI_HT_PRI_LCTR0 4 /* Link Control 0 Register */ |
||
| 455 | #define PCI_HT_PRI_LCNF0 6 /* Link Config 0 Register */ |
||
| 456 | #define PCI_HT_PRI_LCTR1 8 /* Link Control 1 Register */ |
||
| 457 | #define PCI_HT_PRI_LCNF1 10 /* Link Config 1 Register */ |
||
| 458 | #define PCI_HT_PRI_RID 12 /* Revision ID Register */ |
||
| 459 | #define PCI_HT_PRI_LFRER0 13 /* Link Frequency/Error 0 Register */ |
||
| 460 | #define PCI_HT_PRI_LFCAP0 14 /* Link Frequency Capability 0 Register */ |
||
| 461 | #define PCI_HT_PRI_FTR 16 /* Feature Register */ |
||
| 462 | #define PCI_HT_PRI_LFRER1 17 /* Link Frequency/Error 1 Register */ |
||
| 463 | #define PCI_HT_PRI_LFCAP1 18 /* Link Frequency Capability 1 Register */ |
||
| 464 | #define PCI_HT_PRI_ES 20 /* Enumeration Scratchpad Register */ |
||
| 465 | #define PCI_HT_PRI_EH 22 /* Error Handling Register */ |
||
| 466 | #define PCI_HT_PRI_MBU 24 /* Memory Base Upper Register */ |
||
| 467 | #define PCI_HT_PRI_MLU 25 /* Memory Limit Upper Register */ |
||
| 468 | #define PCI_HT_PRI_BN 26 /* Bus Number Register */ |
||
| 469 | #define PCI_HT_PRI_SIZEOF 28 |
||
| 470 | |||
| 471 | /* HyperTransport: Host or Secondary Interface */ |
||
| 472 | #define PCI_HT_SEC_CMD 2 /* Command Register */ |
||
| 473 | #define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */ |
||
| 474 | #define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */ |
||
| 475 | #define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */ |
||
| 476 | #define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */ |
||
| 477 | #define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */ |
||
| 478 | #define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */ |
||
| 479 | #define PCI_HT_SEC_CMD_HIECE 0x0800 /* Host Inbound End of Chain Error */ |
||
| 480 | #define PCI_HT_SEC_CMD_DUL 0x1000 /* Drop on Uninitialized Link */ |
||
| 481 | |||
| 482 | #define PCI_HT_SEC_LCTR 4 /* Link Control Register */ |
||
| 483 | #define PCI_HT_SEC_LCNF 6 /* Link Config Register */ |
||
| 484 | #define PCI_HT_SEC_RID 8 /* Revision ID Register */ |
||
| 485 | #define PCI_HT_SEC_LFRER 9 /* Link Frequency/Error Register */ |
||
| 486 | #define PCI_HT_SEC_LFCAP 10 /* Link Frequency Capability Register */ |
||
| 487 | #define PCI_HT_SEC_FTR 12 /* Feature Register */ |
||
| 488 | #define PCI_HT_SEC_FTR_EXTRS 0x0100 /* Extended Register Set */ |
||
| 489 | #define PCI_HT_SEC_FTR_UCNFE 0x0200 /* Upstream Configuration Enable */ |
||
| 490 | #define PCI_HT_SEC_ES 16 /* Enumeration Scratchpad Register */ |
||
| 491 | #define PCI_HT_SEC_EH 18 /* Error Handling Register */ |
||
| 492 | #define PCI_HT_SEC_MBU 20 /* Memory Base Upper Register */ |
||
| 493 | #define PCI_HT_SEC_MLU 21 /* Memory Limit Upper Register */ |
||
| 494 | #define PCI_HT_SEC_SIZEOF 24 |
||
| 495 | |||
| 496 | /* HyperTransport: Switch */ |
||
| 497 | #define PCI_HT_SW_CMD 2 /* Switch Command Register */ |
||
| 498 | #define PCI_HT_SW_CMD_VIBERR 0x0080 /* VIB Error */ |
||
| 499 | #define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */ |
||
| 500 | #define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */ |
||
| 501 | #define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */ |
||
| 502 | #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */ |
||
| 503 | #define PCI_HT_SW_SWINF 8 /* Switch Info Register */ |
||
| 504 | #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */ |
||
| 505 | #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */ |
||
| 506 | #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */ |
||
| 507 | #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */ |
||
| 508 | #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */ |
||
| 509 | #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */ |
||
| 510 | #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */ |
||
| 511 | #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */ |
||
| 512 | #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */ |
||
| 513 | #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */ |
||
| 514 | #define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */ |
||
| 515 | #define PCI_HT_SW_SIZEOF 24 |
||
| 516 | |||
| 517 | /* Counter indices */ |
||
| 518 | #define PCI_HT_SW_PC_PCR 0x0 /* Posted Command Receive */ |
||
| 519 | #define PCI_HT_SW_PC_NPCR 0x1 /* Nonposted Command Receive */ |
||
| 520 | #define PCI_HT_SW_PC_RCR 0x2 /* Response Command Receive */ |
||
| 521 | #define PCI_HT_SW_PC_PDWR 0x3 /* Posted DW Receive */ |
||
| 522 | #define PCI_HT_SW_PC_NPDWR 0x4 /* Nonposted DW Receive */ |
||
| 523 | #define PCI_HT_SW_PC_RDWR 0x5 /* Response DW Receive */ |
||
| 524 | #define PCI_HT_SW_PC_PCT 0x6 /* Posted Command Transmit */ |
||
| 525 | #define PCI_HT_SW_PC_NPCT 0x7 /* Nonposted Command Transmit */ |
||
| 526 | #define PCI_HT_SW_PC_RCT 0x8 /* Response Command Transmit */ |
||
| 527 | #define PCI_HT_SW_PC_PDWT 0x9 /* Posted DW Transmit */ |
||
| 528 | #define PCI_HT_SW_PC_NPDWT 0xa /* Nonposted DW Transmit */ |
||
| 529 | #define PCI_HT_SW_PC_RDWT 0xb /* Response DW Transmit */ |
||
| 530 | |||
| 531 | /* Base/Limit Range indices */ |
||
| 532 | #define PCI_HT_SW_BLR_BASE0_LO 0x0 /* Base 0[31:1], Enable */ |
||
| 533 | #define PCI_HT_SW_BLR_BASE0_HI 0x1 /* Base 0 Upper */ |
||
| 534 | #define PCI_HT_SW_BLR_LIM0_LO 0x2 /* Limit 0 Lower */ |
||
| 535 | #define PCI_HT_SW_BLR_LIM0_HI 0x3 /* Limit 0 Upper */ |
||
| 536 | |||
| 537 | /* Secondary Base indices */ |
||
| 538 | #define PCI_HT_SW_SB_LO 0x0 /* Secondary Base[31:1], Enable */ |
||
| 539 | #define PCI_HT_SW_S0_HI 0x1 /* Secondary Base Upper */ |
||
| 540 | |||
| 541 | /* HyperTransport: Interrupt Discovery and Configuration */ |
||
| 542 | #define PCI_HT_IDC_IDX 2 /* Index Register */ |
||
| 543 | #define PCI_HT_IDC_DATA 4 /* Data Register */ |
||
| 544 | #define PCI_HT_IDC_SIZEOF 8 |
||
| 545 | |||
| 546 | /* Register indices */ |
||
| 547 | #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */ |
||
| 548 | #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */ |
||
| 549 | #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */ |
||
| 550 | /* Low part (at index) */ |
||
| 551 | #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */ |
||
| 552 | #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */ |
||
| 553 | #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */ |
||
| 554 | #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */ |
||
| 555 | #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */ |
||
| 556 | #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */ |
||
| 557 | /* High part (at index + 1) */ |
||
| 558 | #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */ |
||
| 559 | #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */ |
||
| 560 | #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */ |
||
| 561 | |||
| 562 | /* HyperTransport: Revision ID */ |
||
| 563 | #define PCI_HT_RID_RID 2 /* Revision Register */ |
||
| 564 | #define PCI_HT_RID_SIZEOF 4 |
||
| 565 | |||
| 566 | /* HyperTransport: UnitID Clumping */ |
||
| 567 | #define PCI_HT_UIDC_CS 4 /* Clumping Support Register */ |
||
| 568 | #define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */ |
||
| 569 | #define PCI_HT_UIDC_SIZEOF 12 |
||
| 570 | |||
| 571 | /* HyperTransport: Extended Configuration Space Access */ |
||
| 572 | #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */ |
||
| 573 | #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */ |
||
| 574 | #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */ |
||
| 575 | #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */ |
||
| 576 | #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */ |
||
| 577 | #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */ |
||
| 578 | #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */ |
||
| 579 | #define PCI_HT_ECSA_SIZEOF 12 |
||
| 580 | |||
| 581 | /* HyperTransport: Address Mapping */ |
||
| 582 | #define PCI_HT_AM_CMD 2 /* Command Register */ |
||
| 583 | #define PCI_HT_AM_CMD_NDMA 0x000f /* Number of DMA Mappings */ |
||
| 584 | #define PCI_HT_AM_CMD_IOSIZ 0x01f0 /* I/O Size */ |
||
| 585 | #define PCI_HT_AM_CMD_MT 0x0600 /* Map Type */ |
||
| 586 | #define PCI_HT_AM_CMD_MT_40B 0x0000 /* 40-bit */ |
||
| 587 | #define PCI_HT_AM_CMD_MT_64B 0x0200 /* 64-bit */ |
||
| 588 | |||
| 589 | /* Window Control Register bits */ |
||
| 590 | #define PCI_HT_AM_SBW_CTR_COMP 0x1 /* Compat */ |
||
| 591 | #define PCI_HT_AM_SBW_CTR_NCOH 0x2 /* NonCoherent */ |
||
| 592 | #define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */ |
||
| 593 | #define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */ |
||
| 594 | |||
| 595 | /* HyperTransport: 40-bit Address Mapping */ |
||
| 596 | #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */ |
||
| 597 | #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */ |
||
| 598 | #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */ |
||
| 599 | #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */ |
||
| 600 | #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */ |
||
| 601 | #define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */ |
||
| 602 | #define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */ |
||
| 603 | #define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */ |
||
| 604 | #define PCI_HT_AM40_DMA_SBASE0 18 /* DMA Window Secondary Base 0 Register */ |
||
| 605 | #define PCI_HT_AM40_SIZEOF 12 /* size is variable: 12 + 8 * NDMA */ |
||
| 606 | |||
| 607 | /* HyperTransport: 64-bit Address Mapping */ |
||
| 608 | #define PCI_HT_AM64_IDX 4 /* Index Register */ |
||
| 609 | #define PCI_HT_AM64_DATA_LO 8 /* Data Lower Register */ |
||
| 610 | #define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */ |
||
| 611 | #define PCI_HT_AM64_SIZEOF 16 |
||
| 612 | |||
| 613 | /* Register indices */ |
||
| 614 | #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */ |
||
| 615 | #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */ |
||
| 616 | #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */ |
||
| 617 | #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */ |
||
| 618 | #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */ |
||
| 619 | #define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */ |
||
| 620 | #define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */ |
||
| 621 | #define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */ |
||
| 622 | |||
| 623 | /* HyperTransport: MSI Mapping */ |
||
| 624 | #define PCI_HT_MSIM_CMD 2 /* Command Register */ |
||
| 625 | #define PCI_HT_MSIM_CMD_EN 0x0001 /* Mapping Active */ |
||
| 626 | #define PCI_HT_MSIM_CMD_FIXD 0x0002 /* MSI Mapping Address Fixed */ |
||
| 627 | #define PCI_HT_MSIM_ADDR_LO 4 /* MSI Mapping Address Lower Register */ |
||
| 628 | #define PCI_HT_MSIM_ADDR_HI 8 /* MSI Mapping Address Upper Register */ |
||
| 629 | #define PCI_HT_MSIM_SIZEOF 12 |
||
| 630 | |||
| 631 | /* HyperTransport: DirectRoute */ |
||
| 632 | #define PCI_HT_DR_CMD 2 /* Command Register */ |
||
| 633 | #define PCI_HT_DR_CMD_NDRS 0x000f /* Number of DirectRoute Spaces */ |
||
| 634 | #define PCI_HT_DR_CMD_IDX 0x01f0 /* Index */ |
||
| 635 | #define PCI_HT_DR_EN 4 /* Enable Vector Register */ |
||
| 636 | #define PCI_HT_DR_DATA 8 /* Data Register */ |
||
| 637 | #define PCI_HT_DR_SIZEOF 12 |
||
| 638 | |||
| 639 | /* Register indices */ |
||
| 640 | #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */ |
||
| 641 | #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */ |
||
| 642 | #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */ |
||
| 643 | #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */ |
||
| 644 | #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */ |
||
| 645 | #define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */ |
||
| 646 | |||
| 647 | /* HyperTransport: VCSet */ |
||
| 648 | #define PCI_HT_VCS_SUP 4 /* VCSets Supported Register */ |
||
| 649 | #define PCI_HT_VCS_L1EN 5 /* Link 1 VCSets Enabled Register */ |
||
| 650 | #define PCI_HT_VCS_L0EN 6 /* Link 0 VCSets Enabled Register */ |
||
| 651 | #define PCI_HT_VCS_SBD 8 /* Stream Bucket Depth Register */ |
||
| 652 | #define PCI_HT_VCS_SINT 9 /* Stream Interval Register */ |
||
| 653 | #define PCI_HT_VCS_SSUP 10 /* Number of Streaming VCs Supported Register */ |
||
| 654 | #define PCI_HT_VCS_SSUP_0 0x00 /* Streaming VC 0 */ |
||
| 655 | #define PCI_HT_VCS_SSUP_3 0x01 /* Streaming VCs 0-3 */ |
||
| 656 | #define PCI_HT_VCS_SSUP_15 0x02 /* Streaming VCs 0-15 */ |
||
| 657 | #define PCI_HT_VCS_NFCBD 12 /* Non-FC Bucket Depth Register */ |
||
| 658 | #define PCI_HT_VCS_NFCINT 13 /* Non-FC Bucket Interval Register */ |
||
| 659 | #define PCI_HT_VCS_SIZEOF 16 |
||
| 660 | |||
| 661 | /* HyperTransport: Retry Mode */ |
||
| 662 | #define PCI_HT_RM_CTR0 4 /* Control 0 Register */ |
||
| 663 | #define PCI_HT_RM_CTR_LRETEN 0x01 /* Link Retry Enable */ |
||
| 664 | #define PCI_HT_RM_CTR_FSER 0x02 /* Force Single Error */ |
||
| 665 | #define PCI_HT_RM_CTR_ROLNEN 0x04 /* Rollover Nonfatal Enable */ |
||
| 666 | #define PCI_HT_RM_CTR_FSS 0x08 /* Force Single Stomp */ |
||
| 667 | #define PCI_HT_RM_CTR_RETNEN 0x10 /* Retry Nonfatal Enable */ |
||
| 668 | #define PCI_HT_RM_CTR_RETFEN 0x20 /* Retry Fatal Enable */ |
||
| 669 | #define PCI_HT_RM_CTR_AA 0xc0 /* Allowed Attempts */ |
||
| 670 | #define PCI_HT_RM_STS0 5 /* Status 0 Register */ |
||
| 671 | #define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */ |
||
| 672 | #define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */ |
||
| 673 | #define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */ |
||
| 674 | #define PCI_HT_RM_CTR1 6 /* Control 1 Register */ |
||
| 675 | #define PCI_HT_RM_STS1 7 /* Status 1 Register */ |
||
| 676 | #define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */ |
||
| 677 | #define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */ |
||
| 678 | #define PCI_HT_RM_SIZEOF 12 |
||
| 679 | |||
| 680 | /* PCI Express */ |
||
| 681 | #define PCI_EXP_FLAGS 0x2 /* Capabilities register */ |
||
| 682 | #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ |
||
| 683 | #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ |
||
| 684 | #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ |
||
| 685 | #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ |
||
| 686 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ |
||
| 687 | #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ |
||
| 688 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ |
||
| 689 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ |
||
| 690 | #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
||
| 691 | #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ |
||
| 692 | #define PCI_EXP_DEVCAP 0x4 /* Device capabilities */ |
||
| 693 | #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ |
||
| 694 | #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ |
||
| 695 | #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ |
||
| 696 | #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
||
| 697 | #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
||
| 698 | #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
||
| 699 | #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
||
| 700 | #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
||
| 701 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
||
| 702 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
||
| 703 | #define PCI_EXP_DEVCTL 0x8 /* Device Control */ |
||
| 704 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ |
||
| 705 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
||
| 706 | #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
||
| 707 | #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
||
| 708 | #define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */ |
||
| 709 | #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ |
||
| 710 | #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ |
||
| 711 | #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ |
||
| 712 | #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ |
||
| 713 | #define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */ |
||
| 714 | #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ |
||
| 715 | #define PCI_EXP_DEVSTA 0xa /* Device Status */ |
||
| 716 | #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ |
||
| 717 | #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ |
||
| 718 | #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ |
||
| 719 | #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ |
||
| 720 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
||
| 721 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
||
| 722 | #define PCI_EXP_LNKCAP 0xc /* Link Capabilities */ |
||
| 723 | #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ |
||
| 724 | #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ |
||
| 725 | #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ |
||
| 726 | #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ |
||
| 727 | #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ |
||
| 728 | #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ |
||
| 729 | #define PCI_EXP_LNKCTL 0x10 /* Link Control */ |
||
| 730 | #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ |
||
| 731 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
||
| 732 | #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ |
||
| 733 | #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ |
||
| 734 | #define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */ |
||
| 735 | #define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */ |
||
| 736 | #define PCI_EXP_LNKSTA 0x12 /* Link Status */ |
||
| 737 | #define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */ |
||
| 738 | #define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */ |
||
| 739 | #define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error */ |
||
| 740 | #define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */ |
||
| 741 | #define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */ |
||
| 742 | #define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */ |
||
| 743 | #define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */ |
||
| 744 | #define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */ |
||
| 745 | #define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */ |
||
| 746 | #define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */ |
||
| 747 | #define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */ |
||
| 748 | #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ |
||
| 749 | #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ |
||
| 750 | #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ |
||
| 751 | #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ |
||
| 752 | #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ |
||
| 753 | #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ |
||
| 754 | #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ |
||
| 755 | #define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */ |
||
| 756 | #define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */ |
||
| 757 | #define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */ |
||
| 758 | #define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */ |
||
| 759 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ |
||
| 760 | #define PCI_EXP_SLTCTL_ATNI 0x00C0 /* Attention Indicator Control */ |
||
| 761 | #define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */ |
||
| 762 | #define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */ |
||
| 763 | #define PCI_EXP_SLTSTA 0x1a /* Slot Status */ |
||
| 764 | #define PCI_EXP_RTCTL 0x1c /* Root Control */ |
||
| 765 | #define PCI_EXP_RTCTL_SECEE 0x1 /* System Error on Correctable Error */ |
||
| 766 | #define PCI_EXP_RTCTL_SENFEE 0x1 /* System Error on Non-Fatal Error */ |
||
| 767 | #define PCI_EXP_RTCTL_SEFEE 0x1 /* System Error on Fatal Error */ |
||
| 768 | #define PCI_EXP_RTCTL_PMEIE 0x1 /* PME Interrupt Enable */ |
||
| 769 | #define PCI_EXP_RTSTA 0x20 /* Root Status */ |
||
| 770 | |||
| 771 | /* MSI-X */ |
||
| 772 | #define PCI_MSIX_ENABLE 0x8000 |
||
| 773 | #define PCI_MSIX_MASK 0x4000 |
||
| 774 | #define PCI_MSIX_TABSIZE 0x03ff |
||
| 775 | #define PCI_MSIX_TABLE 4 |
||
| 776 | #define PCI_MSIX_PBA 8 |
||
| 777 | #define PCI_MSIX_BIR 0x7 |
||
| 778 | |||
| 779 | /* Advanced Error Reporting */ |
||
| 780 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
||
| 781 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
||
| 782 | #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
||
| 783 | #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
||
| 784 | #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ |
||
| 785 | #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ |
||
| 786 | #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ |
||
| 787 | #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ |
||
| 788 | #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ |
||
| 789 | #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ |
||
| 790 | #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ |
||
| 791 | #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ |
||
| 792 | #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
||
| 793 | /* Same bits as above */ |
||
| 794 | #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ |
||
| 795 | /* Same bits as above */ |
||
| 796 | #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ |
||
| 797 | #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ |
||
| 798 | #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ |
||
| 799 | #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
||
| 800 | #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ |
||
| 801 | #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ |
||
| 802 | #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
||
| 803 | /* Same bits as above */ |
||
| 804 | #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ |
||
| 805 | #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ |
||
| 806 | #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ |
||
| 807 | #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ |
||
| 808 | #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ |
||
| 809 | #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ |
||
| 810 | #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ |
||
| 811 | #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ |
||
| 812 | #define PCI_ERR_ROOT_STATUS 48 |
||
| 813 | #define PCI_ERR_ROOT_COR_SRC 52 |
||
| 814 | #define PCI_ERR_ROOT_SRC 54 |
||
| 815 | |||
| 816 | /* Virtual Channel */ |
||
| 817 | #define PCI_VC_PORT_REG1 4 |
||
| 818 | #define PCI_VC_PORT_REG2 8 |
||
| 819 | #define PCI_VC_PORT_CTRL 12 |
||
| 820 | #define PCI_VC_PORT_STATUS 14 |
||
| 821 | #define PCI_VC_RES_CAP 16 |
||
| 822 | #define PCI_VC_RES_CTRL 20 |
||
| 823 | #define PCI_VC_RES_STATUS 26 |
||
| 824 | |||
| 825 | /* Power Budgeting */ |
||
| 826 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
||
| 827 | #define PCI_PWR_DATA 8 /* Data Register */ |
||
| 828 | #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ |
||
| 829 | #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ |
||
| 830 | #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ |
||
| 831 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
||
| 832 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
||
| 833 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
||
| 834 | #define PCI_PWR_CAP 12 /* Capability */ |
||
| 835 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
||
| 836 | |||
| 837 | /* |
||
| 838 | * The PCI interface treats multi-function devices as independent |
||
| 839 | * devices. The slot/function address of each device is encoded |
||
| 840 | * in a single byte as follows: |
||
| 841 | * |
||
| 842 | * 7:3 = slot |
||
| 843 | * 2:0 = function |
||
| 844 | */ |
||
| 845 | #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
||
| 846 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
||
| 847 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
||
| 848 | |||
| 849 | /* Device classes and subclasses */ |
||
| 850 | |||
| 851 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
||
| 852 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
||
| 853 | |||
| 854 | #define PCI_BASE_CLASS_STORAGE 0x01 |
||
| 855 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
||
| 856 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
||
| 857 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
||
| 858 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
||
| 859 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
||
| 860 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
||
| 861 | |||
| 862 | #define PCI_BASE_CLASS_NETWORK 0x02 |
||
| 863 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
||
| 864 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
||
| 865 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
||
| 866 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
||
| 867 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
||
| 868 | |||
| 869 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
||
| 870 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
||
| 871 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
||
| 872 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
||
| 873 | |||
| 874 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
||
| 875 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
||
| 876 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
||
| 877 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
||
| 878 | |||
| 879 | #define PCI_BASE_CLASS_MEMORY 0x05 |
||
| 880 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
||
| 881 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
||
| 882 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
||
| 883 | |||
| 884 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
||
| 885 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
||
| 886 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
||
| 887 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
||
| 888 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
||
| 889 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
||
| 890 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
||
| 891 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
||
| 892 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
||
| 893 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
||
| 894 | |||
| 895 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
||
| 896 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
||
| 897 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
||
| 898 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
||
| 899 | |||
| 900 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
||
| 901 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
||
| 902 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
||
| 903 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
||
| 904 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
||
| 905 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
||
| 906 | |||
| 907 | #define PCI_BASE_CLASS_INPUT 0x09 |
||
| 908 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
||
| 909 | #define PCI_CLASS_INPUT_PEN 0x0901 |
||
| 910 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
||
| 911 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
||
| 912 | |||
| 913 | #define PCI_BASE_CLASS_DOCKING 0x0a |
||
| 914 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
||
| 915 | #define PCI_CLASS_DOCKING_OTHER 0x0a01 |
||
| 916 | |||
| 917 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
||
| 918 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
||
| 919 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
||
| 920 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
||
| 921 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
||
| 922 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
||
| 923 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
||
| 924 | |||
| 925 | #define PCI_BASE_CLASS_SERIAL 0x0c |
||
| 926 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
||
| 927 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
||
| 928 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
||
| 929 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
||
| 930 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
||
| 931 | |||
| 932 | #define PCI_CLASS_OTHERS 0xff |
||
| 933 | |||
| 934 | /* Several ID's we need in the library */ |
||
| 935 | |||
| 936 | #define PCI_VENDOR_ID_INTEL 0x8086 |
||
| 937 | #define PCI_VENDOR_ID_COMPAQ 0x0e11 |